Patents by Inventor Shoji Ushio

Shoji Ushio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11078596
    Abstract: A method for evaluating the quality of a SiC single crystal by a non-destructive and simple method; and a method for producing a SiC single crystal ingot with less dislocation and high quality with good reproducibility utilizing the same. The method for evaluating the quality of a SiC single crystal body is based on the graph of a second polynomial equation obtained by differentiating a first polynomial equation, the first polynomial equation approximating the relation between a peak shift value and a position of the measurement point and the peak shift value being obtained by an X-ray rocking curve measurement. The method for producing a SiC single crystal ingot manufactures a SiC single crystal ingot by a sublimation recrystallization method using, as a seed crystal, the SiC single crystal body evaluated by the evaluation method.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 3, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Masashi Nakabayashi, Shoji Ushio
  • Publication number: 20200010974
    Abstract: A method for evaluating the quality of a SiC single crystal by a non-destructive and simple method; and a method for producing a SiC single crystal ingot with less dislocation and high quality with good reproducibility utilizing the same. The method for evaluating the quality of a SiC single crystal body is based on the graph of a second polynomial equation obtained by differentiating a first polynomial equation, the first polynomial equation approximating the relation between a peak shift value and a position of the measurement point and the peak shift value being obtained by an X-ray rocking curve measurement. The method for producing a SiC single crystal ingot manufactures a SiC single crystal ingot by a sublimation recrystallization method using, as a seed crystal, the SiC single crystal body evaluated by the evaluation method.
    Type: Application
    Filed: March 29, 2018
    Publication date: January 9, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Masashi NAKABAYASHI, Shoji USHIO
  • Patent number: 10012675
    Abstract: A standard sample (72) that is a nanometer standard prototype, having a standard length that serves as a length reference, includes a SiC layer in which a step-terrace structure is formed. The height of a step, used as the standard length, is equal to the height of a full unit that corresponds to one periodic of a stack of SiC molecules in a stack direction or equal to the height of a half unit that corresponds to one-half periodic of the stack of SiC molecules in the stack direction. In a microscope such as an STM to be measured in a high-temperature vacuum environment, heating in a vacuum furnace enables surface reconstruction with ordered atomic arrangement, while removing a natural oxide film from the surface, so that accuracy of the height of the step is not degraded. Accordingly, a standard sample usable under a high-temperature vacuum is achieved.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 3, 2018
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Shoji Ushio
  • Patent number: 9029219
    Abstract: A method for manufacturing a semiconductor wafer includes a carbon layer formation step, a through hole formation step, a feed layer formation step, and an epitaxial layer formation step. In the carbon layer formation step, a carbon layer (71) is formed on a surface of a substrate (70) made of polycrystalline SiC. In the through hole formation step, through holes (71c) are formed in the carbon layer (71) formed on the substrate (70). In the feed layer formation step, a Si layer (72) and a 3C—SiC polycrystalline layer (73) are formed on a surface of the carbon layer (71). In the epitaxial layer formation step, the substrate (70) is heated so that a seed crystal made of 4H—SiC single crystal is formed on portions of the surface of the substrate (70) that are exposed through the through holes (71c), and a close-spaced liquid-phase epitaxial growth of the seed crystal is caused to form a 4H—SiC single crystal layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: May 12, 2015
    Assignees: Kwansei Gakuin Educational Foundation, Toyo Tanso Co., Ltd.
    Inventors: Tadaaki Kaneko, Noboru Ohtani, Shoji Ushio, Ayumu Adachi, Satoru Nogami
  • Publication number: 20140319539
    Abstract: A method for manufacturing a semiconductor wafer includes a carbon layer formation step, a through hole formation step, a feed layer formation step, and an epitaxial layer formation step. In the carbon layer formation step, a carbon layer (71) is formed on a surface of a substrate (70) made of polycrystalline SiC. In the through hole formation step, through holes (71c) are formed in the carbon layer (71) formed on the substrate (70). In the feed layer formation step, a Si layer (72) and a 3C—SiC polycrystalline layer (73) are formed on a surface of the carbon layer (71). In the epitaxial layer formation step, the substrate (70) is heated so that a seed crystal made of 4H—SiC single crystal is formed on portions of the surface of the substrate (70) that are exposed through the through holes (71c), and a close-spaced liquid-phase epitaxial growth of the seed crystal is caused to form a 4H—SiC single crystal layer.
    Type: Application
    Filed: August 24, 2012
    Publication date: October 30, 2014
    Applicants: TOYO TANSO CO., LTD., KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Noboru Ohtani, Shoji Ushio, Ayumu Adachi, Satoru Nogami
  • Publication number: 20140317791
    Abstract: A standard sample (72) that is a nanometer standard prototype, having a standard length that serves as a length reference, includes a SiC layer in which a step-terrace structure is formed. The height of a step, used as the standard length, is equal to the height of a full unit that corresponds to one periodic of a stack of SiC molecules in a stack direction or equal to the height of a half unit that corresponds to one-half periodic of the stack of SiC molecules in the stack direction. In a microscope such as an STM to be measured in a high-temperature vacuum environment, heating in a vacuum furnace enables surface reconstruction with ordered atomic arrangement, while removing a natural oxide film from the surface, so that accuracy of the height of the step is not degraded. Accordingly, a standard sample usable under a high-temperature vacuum is achieved.
    Type: Application
    Filed: November 11, 2011
    Publication date: October 23, 2014
    Applicant: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Shoji Ushio