Patents by Inventor Shoji Yo

Shoji Yo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and manufacturing method thereof
    Patent number: 7052955
    Abstract: A method for manufacturing a semiconductor device including an electrode having a lower silicon layer and an upper silicon layer which is formed on the lower silicon layer. A concentration of impurities in the upper silicon layer is higher than a concentration of impurities in the lower silicon layer.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: May 30, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shoji Yo
  • Capacitor structure having hemispherical grains
    Publication number: 20050112818
    Abstract: A first insulating layer is formed on semiconductor substrate, and a trench is formed in the first insulating layer. An amorphous silicon layer doped with impurities is formed on a side and bottom walls of the trench. Next, a resist material is partially filled in the trench so that an upper portion of the amorphous silicon layer is exposed. The exposed portion is implanted with impurity ions. After removal of the resist material, the amorphous silicon layer is heat treated so as to grow hemispherical grains on its surface.
    Type: Application
    Filed: October 27, 2004
    Publication date: May 26, 2005
    Inventors: Yoshiki Nagatomo, Shoji Yo, Osamu Nanba, Hiroaki Uchida, Kazuya Suzuki
  • Method of Fabricating a capacitor structure having hemispherical grains
    Patent number: 6828207
    Abstract: A first insulating layer is formed on semiconductor substrate, and a trench is formed in the first insulating layer. An amorphous silicon layer doped with impurities is formed on a side and bottom walls of the trench. Next, a resist material is partially filled in the trench so that an upper portion of the amorphous silicon layer is exposed. The exposed portion is implanted with impurity ions. After removal of the resist material, the amorphous silicon layer is heat treated so as to grow hemispherical grains on its surface.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: December 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshiki Nagatomo, Shoji Yo, Osamu Nanba, Hiroaki Uchida, Kazuya Suzuki
  • Seniconductor memory device with capacitor
    Publication number: 20030186510
    Abstract: The invention includes a process for the fabrication of semiconductor device, comprising the steps of forming a trench in the interlayer of semiconductor substrate, depositing impurities doped a amorphous silicon served as a lower electrode all over the trench, forming a resist so as to expose the top portion of the amorphous silicon in the trench, etching the amorphous silicon layer except for the trench, implanting impurities into the top portion of the amorphous silicon and growing HSG silicon by means of heat treatment after resist strip.
    Type: Application
    Filed: January 29, 2003
    Publication date: October 2, 2003
    Inventors: Yoshiki Nagatomo, Shoji Yo, Osamu Nanba, Hiroaki Uchida, Kazuya Suzuki
  • Semiconductor device and method in which contact hole is filled with silicon having low impurity concentration
    Patent number: 6589885
    Abstract: A semiconductor device includes a silicon layer. The silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer. A concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: July 8, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shoji Yo
  • Semiconductor memory device and manufacturing method thereof
    Publication number: 20030073281
    Abstract: A semiconductor device includes a silicon layer. The silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer. A concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.
    Type: Application
    Filed: November 25, 2002
    Publication date: April 17, 2003
    Inventor: Shoji Yo