Patents by Inventor Shoki ITO

Shoki ITO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12519308
    Abstract: A semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. The protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: January 6, 2026
    Assignee: KIOXIA CORPORATION
    Inventors: Shigefumi Ishiguro, Yasuhiro Suematsu, Masaru Koyanagi, Maya Inagaki, Kentaro Watanabe, Shoki Ito
  • Publication number: 20250301668
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; conductive layers; pad electrodes; a first wiring and a second wiring provided between the semiconductor substrate and the conductive layers; and via contact electrodes. The pad electrodes include: a first pad electrode having a signal inputted/outputted thereto/therefrom; and a second pad electrode and a third pad electrode applied with voltages. The semiconductor substrate is provided with a first transistor, a second transistor, a first diode, a second diode, and a clamp circuit. A part of the via contact electrodes overlapping the second pad electrode and electrically connected to the first transistor, the first diode, or the clamp circuit are commonly connected to the first wiring. Another part of the via contact electrodes overlapping the third pad electrode and electrically connected to the second transistor, the second diode, or the clamp circuit are commonly connected to the second wiring.
    Type: Application
    Filed: December 13, 2024
    Publication date: September 25, 2025
    Applicant: Kioxia Corporation
    Inventors: Yutaka SHIMIZU, Maya INAGAKI, Masaki NAKAMURA, Masato DOME, Shoki ITO, Kentaro WATANABE
  • Publication number: 20240321865
    Abstract: A semiconductor device includes a first pad to which a high voltage is to be input, a second pad to which a low voltage is to be input, a third pad to which a ground voltage is to be input, and a protection circuit provided between the first pad and the third pad. The protection circuit includes a first protection element group including a plurality of first transistors arranged in a first direction, a second protection element group including a plurality of second transistors arranged in the first direction and disposed apart from the first protection element group in a second direction orthogonal to the first direction, a guard ring provided around the first and second protection element groups, and an intermediate guard ring provided between the first protection element group and the second protection element group and connected to the third pad via a resistance element.
    Type: Application
    Filed: February 28, 2024
    Publication date: September 26, 2024
    Inventors: Syunsuke SASAKI, Shouichi OZAKI, Kenichi SUGAWARA, Hiroaki NAKASA, Takeshi MIYABA, Maya OHSAKA, Shoki ITO
  • Publication number: 20240313527
    Abstract: A semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. The protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.
    Type: Application
    Filed: February 22, 2024
    Publication date: September 19, 2024
    Applicant: Kioxia Corporation
    Inventors: Shigefumi ISHIGURO, Yasuhiro SUEMATSU, Masaru KOYANAGI, Maya INAGAKI, Kentaro WATANABE, Shoki ITO