Patents by Inventor Shom Ponoth

Shom Ponoth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11269789
    Abstract: A device management server computer (“server”) and processing methods are disclosed. In some embodiments, the server is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: March 8, 2022
    Assignee: MERLYN MIND, INC.
    Inventors: Aditya Vempaty, Robert Smith, Shom Ponoth, Sharad Sundararajan, Ravindranath Kokku, Robert Hutter, Satya Nitta
  • Publication number: 20210056046
    Abstract: A device management server computer (“server”) and processing methods are disclosed. In some embodiments, the server is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: ADITYA VEMPATY, ROBERT SMITH, SHOM PONOTH, SHARAD SUNDARARAJAN, RAVINDRANATH KOKKU, ROBERT HUTTER, SATYA NITTA
  • Patent number: 10838881
    Abstract: A device management server computer (“server”) is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 17, 2020
    Assignee: XIO RESEARCH, INC.
    Inventors: Aditya Vempaty, Robert Smith, Shom Ponoth, Sharad Sundararajan, Ravindranath Kokku, Robert Hutter, Satya Nitta
  • Publication number: 20200341912
    Abstract: A device management server computer (“server”) is programmed to manage a plurality of input devices and output devices in a physical room. The server is programmed to analyze media data capturing actions performed by a user in real time as a participant in the physical room, determine how the user would like to connect at least one of the input devices and one of the output devices from the analysis, and enable the connection. The sever is programmed to interpret the actions and derive commands for connecting two or more devices based on predetermined data regarding the input devices and output devices and rules for referring to and connecting these devices.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: ADITYA VEMPATY, ROBERT SMITH, SHOM PONOTH, SHARAD SUNDARARAJAN, RAVINDRANATH KOKKU, ROBERT HUTTER, SATYA NITTA
  • Publication number: 20200211406
    Abstract: A room and activity management server computer (“server”) and processing methods are disclosed. In some embodiments, the server is programmed to manage multi-role activities collaboratively performed by multiple participants in a physical room with multiple media communications. For each activity, the server is configured to assign roles to participants and enforce rules that govern how the participants in given roles interact with one another or engage with the room at given times. In enforcing the rules, the server is programmed to improve such interaction and engagement through multimedia communications.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Inventors: RAVINDRANATH KOKKU, JIEHUA LI, AMOL NAYATE, SATYA V. NITTA, SEAN O'HARA, SHOM PONOTH, SHARAD SUNDARARAJAN
  • Patent number: 10262992
    Abstract: A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 16, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Qing Liu, Shom Ponoth, Akira Ito
  • Patent number: 10236354
    Abstract: A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: March 19, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Qing Liu, Shom Ponoth
  • Patent number: 10192781
    Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Satya V. Nitta, Shom Ponoth
  • Patent number: 10134631
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 10115821
    Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 30, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shom Ponoth, Akira Ito, Qing Liu
  • Publication number: 20180286858
    Abstract: A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Qing LIU, Shom PONOTH, Akira ITO
  • Publication number: 20180122942
    Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.
    Type: Application
    Filed: December 19, 2016
    Publication date: May 3, 2018
    Applicant: Broadcom Corporation
    Inventors: Shom PONOTH, Akira Ito, Qing Liu
  • Patent number: 9953978
    Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 24, 2018
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Kisik Choi, Su Chen Fan, Shom Ponoth
  • Publication number: 20180033860
    Abstract: A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source I drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 1, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd .
    Inventors: Qing Liu, Shom Ponoth
  • Patent number: 9825141
    Abstract: A three dimensional monolithic LDMOS transistor implements a drain structure vertically disposed above a level of the structure that includes a drain connection of the transistor. Displacing the drain structure vertically, out of the plane or level of the gate and source/drain connections, creates a three dimensional structure for the transistor. One result is that the transistor consumes far less lateral area on the substrate. The reduction in lateral area in turn provides benefits such as allowing transistors to be more densely arranged on the substrate and allowing additional devices of other types to be formed on the substrate.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 21, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Qing Liu, Shom Ponoth
  • Patent number: 9799524
    Abstract: A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Akira Ito, Shom Ponoth
  • Patent number: 9793378
    Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 17, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Nicolas Loubet, Shom Ponoth, Prasanna Khare, Qing Liu, Balasubramanian Pranatharthiharan
  • Patent number: 9768055
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 19, 2017
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION, COMMISSASRIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES, (CEA)
    Inventors: Qing Liu, Nicolas Loubet, Prasanna Khare, Shom Ponoth, Maud Vinet, Bruce Doris
  • Patent number: 9741722
    Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.
    Type: Grant
    Filed: October 3, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, Jr., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan, Shom Ponoth, Kern Rim, Kehan Tian, Reinaldo A. Vega
  • Patent number: 9711503
    Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 18, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Shom Ponoth, Juntao Li