Abstract: A method of customizing contextual controls of a remote-control unit (RCU) having a plurality of user interface elements is disclosed. A processor within the RCU receives context information from an integrated output device that includes an output mechanism, the context information being related to an active application being run on the integrated output device and an active object being presented by the active application. The processor determines a set of actions that can be performed on the active object within the active application. The processor dynamically maps actions to user interface elements of the RCU based on the context information. The processor receives a selection of a user interface element and sends a request from the RCU to the integrated output device specifying an action mapped to the user interface element to be performed on the active object and the active application.

Abstract: A method performed by a remote-control unit (RCU) of managing a content transfer to or from integrated output devices (IODs) in a physical room is disclosed. The content transfer involves moving application context of a computer application with which a user can interact, which includes a computer object being operated on and relevant metadata. The RCU is programmed to recognize simple user instructions for the content transfer and perform the content transfer from a source device to a target device in real time, regardless of data transfer protocols specific to computer applications. Specifically, the RCU is programmed to obtain source data from the source device, generate updated source data by combining the source data with one or more commands specifying how the source data is to be handled based on a session mode indicating a type of activity being performed in the physical room, and transmit the updated source data to the target device for further user interaction.

Abstract: A method of managing human-computer interaction using a remote-control unit (RCU) is disclosed. A processor within the RCU receives sensor data from a plurality of sensors within the RCU. The processor determines attributes of the RCU based on the sensor data, the attributes including at least a first user of the RCU and a position and orientation of the RCU in a physical room. The processor determines a use mode of the RCU based on the attributes. The use mode is mapped to a set of actions to be performed on a set of input/output (I/O) devices. Each action is mapped to one or more interactions with the RCU. Responsive to the processor detecting a user interaction with the RCU that is mapped to an action in the set of actions, the processor causes the action to be performed on one or more I/O devices.

Abstract: A method of customizing contextual controls of a remote-control unit (RCU) having a plurality of user interface elements is disclosed. A processor within the RCU receives context information from an integrated output device that includes an output mechanism, the context information being related to an active application being run on the integrated output device and an active object being presented by the active application. The processor determines a set of actions that can be performed on the active object within the active application. The processor dynamically maps actions to user interface elements of the RCU based on the context information. The processor receives a selection of a user interface element and sends a request from the RCU to the integrated output device specifying an action mapped to the user interface element to be performed on the active object and the active application.

Abstract: A device management server computer (“server”) has a media-only interface to a device and transmits a device identifier to the device over the interface, the device identifier having embedded network information sufficient to enable the device to establish a separate connection to the server over a communication link such as a wireless network. An application on the device retrieves the device identifier, extracts the network information, and uses the network information to establish the separate connection over the communication link. The device identifier can be part of an EDID provided over an HDMI interface. Instructions transmitted over the separate connection can be used to control transmission of media over the media-only interface.

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract: Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.

Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.

Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.

Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.