Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.

Abstract: A method includes, in response to receiving an instruction to perform a first operation on first data stored in a memory device, obtaining first compression metadata from the memory device based on an address for the first data, and reducing a number of operations in a set of operations based on the first operation and one or more matching addresses, the one or more matching addresses corresponding to second compression metadata matching the first compression metadata.

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

Abstract: Technology for asynchronous communication including a wired channel, a sender controller, and a receiver controller is disclosed. The sender controller can be configured to send multiple request signals up to a predefined limit on the output request port paired with multiple data blocks sent on the data before receiving an acknowledgment signal on the output acknowledge port. At least one combination of any of the input channel, the sender controller, the output channel, and the receiver controller can be configured to operate within at least one time constraint to avoid stalling an asynchronous flow control.

Abstract: Technology for asynchronous communication including a wired channel, a sender controller, and a receiver controller is disclosed. The sender controller can be configured to send multiple request signals up to a predefined limit on the output request port paired with multiple data blocks sent on the data before receiving an acknowledgment signal on the output acknowledge port. At least one combination of any of the input channel, the sender controller, the output channel, and the receiver controller can be configured to operate within at least one time constraint to avoid stalling an asynchronous flow control.