Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.

Abstract: Methods for dynamically programming a microphone are provided. The method, adopted by a microphone system including a first microphone device and a host device connected thereto, includes: transmitting, by the host device, a command message to the first microphone device; receiving, by the first microphone device, a command message from the host device; decoding, by the first microphone device, the command message; dynamically performing, by the first microphone device, an operation based on the decoded command message to generate first data; and receiving, by the host device, first data from the first microphone device.

Abstract: Methods and apparatus are disclosed for controlling power distribution during transitory power-up period of multi-domain electronic circuits that are supplied by multiple power supplies. The power distribution is controlled by self-regulating power control circuits that operate based on power-up sequencing requirements. Described embodiments of the invention illustrate examples of power-switch and power-switch controller circuits used as elements of the power control circuitry.

Abstract: Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.

Abstract: Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.

Abstract: Methods and apparatus are disclosed for controlling power distribution during transitory power-up period of multi-domain electronic circuits that are supplied by multiple power supplies. The power distribution is controlled by self-regulating power control circuits that operate based on power-up sequencing requirements. Described embodiments of the invention illustrate examples of power-switch and power-switch controller circuits used as elements of the power control circuitry.