Patents by Inventor Shoshi Yasunaga

Shoshi Yasunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6756660
    Abstract: A lead frame for a semiconductor device. The lead frame has opposite first and second sides bounded respectively by first and second parallel reference planes between which a thickness is defined. The lead frame has a support with a surface at the first side of the lead frame for receiving a semiconductor chip. A plurality of leads are spaced from the support to be electrically connected to a semiconductor chip on the support. A first lead in the plurality of leads has a length between first and second ends and a width taken transversely to the length. The first end of the first lead has a first region that has a thickness less than the thickness of the first lead at the second end of the first lead so that at least a part of the first region is offset from the second reference plane toward the first reference plane. The first end of the first lead has at least a first protrusion projecting away from the first reference plane.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: June 29, 2004
    Assignee: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi, Hiroaki Narimatsu
  • Patent number: 6700186
    Abstract: A lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semiconductor chip and at least one lead space from the support. The sheet has a tie bar network which connects a) the support to the at least one lead on each of the first and second lead frames and b) the first and second lead frames, each to the other. The sheet has a dividing line along which the sheet can be cut to separate the first and second lead frames from each other. The tie bar network consists of at least one tie bar extending along a substantial length of the dividing line. The support has a first thickness between the oppositely facing sides of the sheet. The at least one tie bar has a second thickness between the oppositely facing sides of the sheet over a substantial length of the dividing line that is less than the first thickness.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: March 2, 2004
    Assignee: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Hideshi Hanada, Takahiro Ishibashi, Jun Sugimoto, Yuichi Dohki, Hitoshi Etoh
  • Publication number: 20030155634
    Abstract: A lead frame for a semiconductor device. The lead frame has opposite first and second sides bounded respectively by first and second parallel reference planes between which a thickness is defined. The lead frame has a support with a surface at the first side of the lead frame for receiving a semiconductor chip. A plurality of leads are spaced from the support to be electrically connected to a semiconductor chip on the support. A first lead in the plurality of leads has a length between first and second ends and a width taken transversely to the length. The first end of the first lead has a first region that has a thickness less than the thickness of the first lead at the second end of the first lead so that at least a part of the first region is offset from the second reference plane toward the first reference plane. The first end of the first lead has at least a first protrusion projecting away from the first reference plane.
    Type: Application
    Filed: December 18, 2002
    Publication date: August 21, 2003
    Applicant: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi, Hiroaki Narimatsu
  • Patent number: 6607940
    Abstract: A method of manufacturing semiconductor devices. The method includes the steps of: providing a lead frame assembly having oppositely facing first and second sides; mounting a first semiconductor chip on the first side of the lead frame assembly; mounting a second semiconductor chip on the second side of the lead frame assembly; electrically connecting the first semiconductor chip to a first lead on the lead frame assembly; electrically connecting the second semiconductor chip to a second lead on the lead frame assembly; applying sealing resin to the first and second sides of the lead frame assembly with the first and second semiconductor chips mounted thereon; and after applying sealing resin, separating the lead frame assembly into first and second semiconductor devices. The first semiconductor device consists of a first portion of the lead frame assembly, the first semiconductor chip thereon, and the first lead electrically connected to the first semiconductor chip.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: August 19, 2003
    Assignee: Mitsui High-tec Inc.
    Inventor: Shoshi Yasunaga
  • Publication number: 20030096456
    Abstract: A method of manufacturing a semiconductor device. The method includes the steps of: providing a lead frame assembly with joined first and second unit lead frames, with the first unit lead frame having a first support and a plurality of leads and the second unit lead frame having a second support and a plurality of leads; mounting operating components on the first and second unit lead frames; applying a sealing composition over the lead frame assembly and the operating components to define a semiconductor preassembly; cutting the semiconductor preassembly so as to define first and second semiconductor devices, with the first and second semiconductor devices having first and second exposed edges respectively defined by cutting of the semiconductor preassembly; and moving at least the first semiconductor device against another element to break loose flash on the first exposed edge.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 22, 2003
    Applicant: Mitsui High-tec Inc.
    Inventors: Shoshi Yasunaga, Hiroaki Narimatsu, Atsushi Fukui
  • Patent number: 6566740
    Abstract: A lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: May 20, 2003
    Assignee: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Jun Sugimoto
  • Patent number: 6563199
    Abstract: A semiconductor device having a unit lead frame defining a support with a peripheral edge and a first lead spaced from the peripheral edge. The first lead has a recess formed therein. A semiconductor chip is provided on the support. A conductive element electrically connects between the semiconductor chip and the first lead. The resin layer on the semiconductor chip and the first lead extends into the recess. The invention is also directed to a unit lead frame that is part of the semiconductor device, a lead frame incorporating a plurality of unit lead frames, and a method of manufacturing semiconductor devices.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: May 13, 2003
    Assignee: Mitsui High-tec Inc.
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi
  • Publication number: 20020079561
    Abstract: A lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semiconductor chip and at least one lead space from the support. The sheet has a tie bar network which connects a) the support to the at least one lead on each of the first and second lead frames and b) the first and second lead frames, each to the other. The sheet has a dividing line along which the sheet can be cut to separate the first and second lead frames from each other. The tie bar network consists of at least one tie bar extending along a substantial length of the dividing line. The support has a first thickness between the oppositely facing sides of the sheet. The at least one tie bar has a second thickness between the oppositely facing sides of the sheet over a substantial length of the dividing line that is less than the first thickness.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 27, 2002
    Inventors: Shoshi Yasunaga, Hideshi Hanada, Takahiro Ishibashi, Jun Sugimoto, Yuichi Dohki, Hitoshi Etoh
  • Publication number: 20010044169
    Abstract: A semiconductor device having a unit lead frame defining a support with a peripheral edge and a first lead spaced from the peripheral edge. The first lead has a recess formed therein. A semiconductor chip is provided on the support. A conductive element electrically connects between the semiconductor chip and the first lead. The resin layer on the semiconductor chip and the first lead extends into the recess. The invention is also directed to a unit lead frame that is part of the semiconductor device, a lead frame incorporating a plurality of unit lead frames, and a method of manufacturing semiconductor devices.
    Type: Application
    Filed: March 20, 2001
    Publication date: November 22, 2001
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi
  • Publication number: 20010041386
    Abstract: A method of manufacturing semiconductor devices. The method includes the steps of: providing a lead frame assembly having oppositely facing first and second sides; mounting a first semiconductor chip on the first side of the lead frame assembly; mounting a second semiconductor chip on the second side of the lead frame assembly; electrically connecting the first semiconductor chip to a first lead on the lead frame assembly; electrically connecting the second semiconductor chip to a second lead on the lead frame assembly; applying sealing resin to the first and second sides of the lead frame assembly with the first and second semiconductor chips mounted thereon; and after applying sealing resin, separating the lead frame assembly into first and second semiconductor devices. The first semiconductor device consists of a first portion of the lead frame assembly, the first semiconductor chip thereon, and the first lead electrically connected to the first semiconductor chip.
    Type: Application
    Filed: February 21, 2001
    Publication date: November 15, 2001
    Inventor: Shoshi Yasunaga
  • Publication number: 20010040276
    Abstract: A lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.
    Type: Application
    Filed: March 20, 2001
    Publication date: November 15, 2001
    Inventors: Shoshi Yasunaga, Jun Sugimoto