Patents by Inventor Shoso Nambu

Shoso Nambu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060267015
    Abstract: A gate electrode of a thin film transistor is composed by a three layer structure obtained by laminating a titanium nitride layer as an upper layer on an aluminum layer as a base layer and by laminating an unalloyed titanium layer as a lower layer under the base layer. An ion implantation is used as an ion doping into a source region and drain region as an active layer of the thin film transistor. The source region and the drain region are annealed at a low temperature of 350° C. to 450° C. to be activated. A chemical reaction between the base layer and the upper layer and between the base layer and the lower layer can be suppressed. The rise of the resistance value in the gate electrode can be suppressed. The resistance of the gate electrode can be reduced. The fluctuation of the threshold voltage of the thin film transistor can be suppressed.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 30, 2006
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Hiroshi Omi, Mamoru Furuta, Shoso Nambu, Takayoshi Dohi, Akihiro Takami, Shuji Manda, Hajime Inoue