Patents by Inventor Shota Hasegawa

Shota Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230381659
    Abstract: A non-transitory storage medium storing a computer program for causing a computer to calculate an action of each object within a field to cause a match between the user and the opponent to proceed, and for providing the game in which the first turn of an offense and the second turn of a defense are switched between the user and the opponent based on a calculation result of the action, wherein the computer program causes the computer to serve as a selection opportunity provision unit that suspends the action of each object in conjunction with switching of the turns and provides an opportunity of selection regarding the match to the user, and a calculation control unit that controls calculation of the match so that the selection by the user is reflected in the calculation of the match within a target period until switching of the turns occurs next.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 30, 2023
    Applicant: KONAMI DIGITAL ENTERTAIMENT CO., LTD.
    Inventors: Kazuma TSURUMOTO, Koji ISHII, Syogo YAMAZAKI, Taemin KIM, Yoshimasa SAITO, Yaojen CHANG, Tomohiro NAKADA, Osamu IKEDA, Shota HASEGAWA, Taito ITO, Kuka LEE, Satoshi HIGASHIDA, Yasunori KOBAYASHI, Tomohisa KOIKE, Taro MURAKAMI, Yumi KATO, Chikako IIZUKA, Shuichiro YOSHIMURA
  • Publication number: 20230194937
    Abstract: A display area formed in an overlapping area of a TFT substrate and a counter substrate, a terminal area formed on the TFT substrate in which the counter substrate does not overlap, and a side of the counter substrate adjacent to the terminal area extending in a first direction, in which a basic potential terminal to be connected to a basic potential, and terminal wirings are formed in the terminal area, an IC driver is installed on the terminal area, an upper polarizing plate having a transparent conductive adhesive is adhered to the counter substrate, the upper polarizing plate extends in a direction perpendicular to the first direction, and covers a part of the terminal area, the basic potential terminal is electrically connected with the transparent conductive adhesive of the upper polarizing plate via a conductive element, and the upper polarizing plate covers the driver IC.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Inventors: Shota HASEGAWA, Shinichiro TANAKA
  • Patent number: 8434036
    Abstract: An arithmetic-program conversion apparatus includes: a program storage section storing an arithmetic program describing a circuit by a logical expression including a plurality of input and output variables, and operators; if the expression has three input variables or more, an intermediate-variable generation section generating an intermediate variable for converting the expression into a plurality of binomials including input and output variables; if the intermediate variable is generated, an expression conversion section converting the logical expression into a plurality of binomials including a binomial for obtaining the intermediate variable and a binomial obtaining the output variable from the intermediate variable; if a plurality of binomials are generated, an expression update section updating the stored original expression; a bit-width determination section determining bit widths of the output, input, and intermediate variables of the expression; and a bit-width storage section storing the bit widths
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: April 30, 2013
    Assignee: Sony Corporation
    Inventor: Shota Hasegawa
  • Publication number: 20100185836
    Abstract: An arithmetic-program conversion apparatus includes: a program storage section storing an arithmetic program describing a circuit by a logical expression including a plurality of input and output variables, and operators; if the expression has three input variables or more, an intermediate-variable generation section generating an intermediate variable for converting the expression into a plurality of binomials including input and output variables; if the intermediate variable is generated, an expression conversion section converting the logical expression into a plurality of binomials including a binomial for obtaining the intermediate variable and a binomial obtaining the output variable from the intermediate variable; if a plurality of binomials are generated, an expression update section updating the stored original expression; a bit-width determination section determining bit widths of the output, input, and intermediate variables of the expression; and a bit-width storage section storing the bit widths
    Type: Application
    Filed: January 19, 2010
    Publication date: July 22, 2010
    Applicant: Sony Corporation
    Inventor: Shota Hasegawa