Abstract: The combine may include a threshing tank that is configured to store a threshing product obtained by the threshing device and includes a lower tapered portion formed in a bottom portion. A bottom screw is provided inside the lower tapered portion and configured to discharge the threshing product from the threshing tank. A threshing discharge device is connected to the bottom screw and configured to convey the threshing product from the bottom screw and discharge the threshing product in a body outward direction. The threshing tank includes an inspection port formed in a bottom section of the lower tapered portion, and a lid configured to open and close the inspection port, and the lid opens and closes by swinging upward and downward about a swing axis that is not parallel with a screw axis of the bottom screw.

Abstract: Inhibition of movement of charges in a semiconductor element (100) formed by growing a group III-V compound semiconductor layer on a silicon substrate (110) is prevented. The semiconductor element (100) includes a silicon substrate (110), a first compound semiconductor layer (140), a second compound semiconductor layer (150), and an electrode (121). The first compound semiconductor layer (140) is formed on the silicon substrate (110). The second compound semiconductor layer (150) is stacked on the first compound semiconductor layer (140). The electrode (121) is disposed on the silicon substrate (110) and controls movement of charges between the silicon substrate (110) and the second compound semiconductor layer (150) via the first compound semiconductor layer (140).

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the semiconductor device is described.

Abstract: A semiconductor device including a nonvolatile memory and the fabrication method of the semiconductor device is described.

Abstract: Memory cells each having a floating gate (4), control gate (6), and source and drain diffusion layers (7a, 7b) are formed on a silicon substrate (1). A silicon nitride film (10) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film (11) by plasma CVD is formed to cover a memory cell array, and silicon oxide films (12a, 12b) are made on the silicon nitride film (11) to form an inter-layer insulating film. A common source line (13) connected to the source diffusion layer 7a is formed to embed in the silicon oxide film (12a), and a bit line (14) connected to the drain diffusion layer (7b) is formed on the silicon oxide film (12b).

Abstract: Memory cells each having a floating gate (4), control gate (6), and source and drain diffusion layers (7a, 7b) are formed on a silicon substrate (1). A silicon nitride film (10) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film (11) by plasma CVD is formed to cover a memory cell array, and silicon oxide films (12a, 12b) are made on the silicon nitride film (11) to form an inter-layer insulating film. A common source line (13) connected to the source diffusion layer 7a is formed to embed in the silicon oxide film (12a), and a bit line (14) connected to the drain diffusion layer (7b) is formed on the silicon oxide film (12b).

Abstract: Memory cells each having a floating gate (4), control gate (6), and source and drain diffusion layers (7a, 7b) are formed on a silicon substrate (1). A silicon nitride film (10) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film (11) by plasma CVD is formed to cover a memory cell array, and silicon oxide films (12a, 12b) are made on the silicon nitride film (11) to forman inter-layer insulating film. Acommon source line (13) connected to the source diffusion layer 7a is formed to embed in the silicon oxide film (12a), and a bit line (14) connected to the drain diffusion layer (7b) is formed on the silicon oxide film (12b).