Abstract: A parallel driving device that drives parallel-connected semiconductor elements includes a control unit and a gate driving circuit. The control unit detects a temperature difference between the semiconductor elements on the basis of detected values by temperature sensors that detect temperatures of the individual semiconductor elements. The control unit generates a control signal for changing the timing at which to turn on a first semiconductor element specified from the semiconductor elements on the basis of the temperature difference. The gate driving circuit generates a first driving signal for driving the semiconductor elements, and generates a second driving signal that is the first driving signal delayed on the basis of the control signal, and applies the second driving signal to the first semiconductor element.

Abstract: The purpose of the invention is to provide a porous hollow-fiber membrane containing a regenerated cellulose and having an elastic limit pressure of 200 kPa or more.

Abstract: A porous membrane comprising a thermoplastic resin, and having a densely structured layer, wherein the ratio of ? crystal strength to ? crystal strength of the thermoplastic resin in the densely structured layer is 5.0 or more.

Abstract: An authentication system is provided with a server device for generating a random number used for authentication and check data obtained by encrypting the random number using an encryption key, an authentication device for authenticating a device to be authenticated by transmitting the random number transmitted from the server device to the device to be authenticated and comparing reply data transmitted from the device to be authenticated with check data transmitted from the server device, and the device to be authenticated for encrypting the random number transmitted from the authentication device using the encryption key and transmitting the encrypted random number as reply data.

Abstract: When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: To provide a contactless communication system that can reduce a time required to complete an identification of all data carriers that exist around a reader/writer and thus attempt to speed up its processing. According to the contactless communication system, multiple data carriers detect a response requesting command from an access device and send back an individual response signal for one-bit information to the access device at a time that is ordered based on a portion of each carrier's identification information, and the access device monitors individual slots for the response signals and determines that detection of the presence of data carriers is completed when it has obtained individual signals from the data carriers, thereby reducing the time required to complete the identification of all data carriers.

Abstract: In a controller device, when a first transmitting signal is at a “L” level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a “H” level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a “L” level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a “H” level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit.

Abstract: A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.

Abstract: To realize a stable communication without an erroneous data demodulation due to the influence of a skew between signals in a two-wire type data communication for performing a data communication and supplying clocks and electric power by first and second signal lines between a controller and a data storage device. When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: To provide a contactless communication system that can reduce a time required to complete an identification of all data carriers that exist around a reader/writer and thus attempt to speed up its processing. According to the contactless communication system, multiple data carriers detect a response requesting command from an access device and send back an individual response signal for one-bit information to the access device at a time that is ordered based on a portion of each carrier's identification information, and the access device monitors individual slots for the response signals and determines that detection of the presence of data carriers is completed when it has obtained individual signals from the data carriers, thereby reducing the time required to complete the identification of all data carriers.

Abstract: In a controller device, when a first transmitting signal is at a “L” level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a “H” level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a “L” level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a “H” level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit.

Abstract: A state control circuit (107) gives an inactive state control signal (S2) to a CPU (105) and an active state control signal (S3) to a data transmission circuit (102). In response to this, the CPU (105) goes into the halt state and the data transmission circuit (102) goes into the receive state. When receive processing is completed, the state control circuit (107) gives an active state control signal (S2) to the CPU (105). In response to this, the CPU (105) restores from the halt state to the operative state. The CPU (105) gives an instruction signal (CMD2) to the state control circuit (107). The state control circuit (107) gives an inactive state control signal (S3) to the data transmission circuit (102). In response to this, the data transmission circuit (102) goes into the halt state.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.