Patents by Inventor Shota NOTE

Shota NOTE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit and semiconductor device
    Patent number: 10535385
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Tsuji, Hiroki Ohkouchi, Shota Note, Masashi Nakata, Yohei Yasuda
  • SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    Publication number: 20190348093
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro TSUJI, Hiroki OHKOUCHI, Shota NOTE, Masashi NAKATA, Yohei YASUDA
  • Semiconductor integrated circuit and semiconductor device
    Patent number: 10403341
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro Tsuji, Hiroki Ohkouchi, Shota Note, Masashi Nakata, Yohei Yasuda
  • SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    Publication number: 20190080734
    Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Nobuhiro TSUJI, Hiroki OHKOUCHI, Shota NOTE, Masashi NAKATA, Yohei YASUDA