Abstract: An object of the present invention is to provide a semiconductor device capable of simplifying a trimming operation. A semiconductor device according to an embodiment includes a power supply circuit and a trimming circuit. The power supply circuit includes a reference voltage generation circuit that generates a plurality of reference voltages used at the time of a trimming operation, and a voltage generation circuit that generates a plurality of power supply voltages used by a semiconductor storage device. The semiconductor device adjusts a specific reference voltage using an external reference voltage at the time of the trimming operation, and then determines trimming codes corresponding to the adjustment amounts of the power supply voltages using a plurality of reference voltages generated using the adjusted specific reference voltage and a plurality of power supply voltages corresponding to the reference voltages.

Abstract: An object of the present invention is to provide a semiconductor device capable of simplifying a trimming operation. A semiconductor device according to an embodiment includes a power supply circuit and a trimming circuit. The power supply circuit includes a reference voltage generation circuit that generates a plurality of reference voltages used at the time of a trimming operation, and a voltage generation circuit that generates a plurality of power supply voltages used by a semiconductor storage device. The semiconductor device adjusts a specific reference voltage using an external reference voltage at the time of the trimming operation, and then determines trimming codes corresponding to the adjustment amounts of the power supply voltages using a plurality of reference voltages generated using the adjusted specific reference voltage and a plurality of power supply voltages corresponding to the reference voltages.

Abstract: A semiconductor device includes a memory unit and a control unit which controls the memory unit. The memory unit a memory which is configured with a non-volatile memory device, and stores setting information necessary for rewriting, a first control circuit which has a first register and a rewrite end flag, and a power source circuit which generates a rewrite voltage. The control unit includes a second control circuit which has a rewrite start flag, a counter which measures a rewrite voltage application time based on the rewrite start flag and the rewrite end flag, and a second register which stores a next rewrite voltage based on the rewrite voltage application time. When a command for rewriting the memory is received, the control unit reads the setting information necessary for rewriting from the memory, and writes it back to the first register.

Abstract: A semiconductor device includes a memory unit and a control unit which controls the memory unit. The memory unit a memory which is configured with a non-volatile memory device, and stores setting information necessary for rewriting, a first control circuit which has a first register and a rewrite end flag, and a power source circuit which generates a rewrite voltage. The control unit includes a second control circuit which has a rewrite start flag, a counter which measures a rewrite voltage application time based on the rewrite start flag and the rewrite end flag, and a second register which stores a next rewrite voltage based on the rewrite voltage application time. When a command for rewriting the memory is received, the control unit reads the setting information necessary for rewriting from the memory, and writes it back to the first register.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: Data which sets up operation parameters, etc. of an internal circuit is supplied stably over a long period of time. In a cell array in which MRAM cells are arranged, read/write of test data is performed in a PROM mode. Finally, data writing is specifically performed to the memory cells in an OTP mode.

Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.

Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.