Patents by Inventor Shota SHINOHARA
Shota SHINOHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11643739Abstract: Provided are an anode for an ion exchange membrane electrolyzer which enables an aqueous solution of an alkali metal chloride to be electrolyzed at a lower voltage than a conventional anode and allows the concentration of an impurity gas included in an anode gas to be reduced and an ion exchange membrane electrolyzer using the same. The anode is an anode for an ion exchange membrane electrolyzer to be used in an ion exchange membrane electrolyzer that is separated by an ion exchange membrane into an anode chamber and a cathode chamber. The anode for an ion exchange membrane electrolyzer comprises at least one perforated flat metal plate 1 (expanded metal 1) and the thickness of the perforated flat metal plate 1 (expanded metal 1) ranges from 0.1 to 0.5 mm and the ratio of the short way SW to the long way LW (SW/LW) ranges from 0.45 to 0.55. The short way SW is preferably not more than 3.0 mm.Type: GrantFiled: January 15, 2015Date of Patent: May 9, 2023Assignees: TOSOH CORPORATION, THYSSENKRUPP NUCERA JAPAN LTD.Inventors: Terumi Hashimoto, Koji Kawanishi, Fumio Sadahiro, Shota Shinohara, Sachio Kaneko
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Publication number: 20200169324Abstract: An optical transmission apparatus includes a detecting circuit configured to detect one or more empty slots in which a data signal is not accommodated in a plurality of slots included in a frame, a frame processing circuit configured to reduce size of the frame by deleting the one or more empty slots from the frame based on a detection result of the one or more empty slots and closing up gaps between remaining slots in the plurality of slots, and an optical modulation processing circuit configured to carry out multi-level modulation of the frame at a bit rate according to size of the frame after reduction.Type: ApplicationFiled: November 22, 2019Publication date: May 28, 2020Applicant: FUJITSU LIMITEDInventors: Kunihiko YANAGIKUIDA, Shota Shinohara, Hisayuki Ojima, Toshihiro Suzuki, Taketo Endo, Hayato Furukawa
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Patent number: 9918147Abstract: A transmission apparatus includes: a plurality of first devices; and a second device configured to output a data signal shared by the plurality of first devices and respective first clock signals to each of the plurality of first devices, and to control the plurality of first devices individually based on the respective first clock signals.Type: GrantFiled: April 2, 2015Date of Patent: March 13, 2018Assignee: FUJITSU LIMITEDInventor: Shota Shinohara
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Patent number: 9762986Abstract: There is provided a frame converter that writes input data included in an input frame to a buffer to accumulate the input data and outputs data read from the buffer as output data included in an output frame, the frame converter includes a setting unit configured to set a time interval from start of resizing of data rate of the input data to start of resizing of data rate of the output data when resizing of an accumulation amount in the buffer is performed in which data rates of the input data and the output data vary, and an adjustment unit configured to adjust to approximate the data rate of the output data to the data rate of the input data after the time interval has elapsed since the start of resizing of data rate of the input data.Type: GrantFiled: September 10, 2013Date of Patent: September 12, 2017Assignee: FUJITSU LIMITEDInventors: Makoto Shimizu, Shota Shinohara
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Publication number: 20170155457Abstract: A synchronization detection method executed by a processor included in a transmission apparatus, the synchronization detection method includes receiving a frame in accordance with a predetermined timing; calculating an unmatched bit number that indicates a number of unmatched bits between a bit stream of the received frame and an expected bit stream that indicates a bit stream that has been expected to be received; acquiring an accumulated number by accumulating the unmatched bit number at the predetermined timing; determining whether the received frame is synchronized with a predetermined signal by comparing the accumulated number and a predetermined threshold; and starting processing for establishing synchronization between the received frame and the predetermined signal when it is determined that the received frame is not synchronized with the predetermined signal.Type: ApplicationFiled: September 21, 2016Publication date: June 1, 2017Applicant: FUJITSU LIMITEDInventor: Shota Shinohara
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Patent number: 9584307Abstract: A transmission apparatus includes: a plurality of logical lanes; a receiver configured to receive a signal including synchronization information of a frame; a distributor configured to divide data included in the received signal into frame elements and cause the plurality of logical lanes to store the data; and a transmitter configured to transmit the data stored in the logical lanes to lines corresponding to the logical lanes. When the data is stored in the plurality of logical lanes, the distributor groups the logical lanes into a plurality of groups and associates the frame elements with the synchronization information.Type: GrantFiled: January 12, 2015Date of Patent: February 28, 2017Assignee: FUJITSU LIMITEDInventors: Hayato Furukawa, Wataru Odashima, Shota Shinohara, Toru Katagiri
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Patent number: 9525509Abstract: A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots.Type: GrantFiled: March 1, 2013Date of Patent: December 20, 2016Assignee: FUJITSU LIMITEDInventors: Hidetaka Kawahara, Junichi Sugiyama, Wataru Odashima, Shota Shinohara, Hiroyuki Homma
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Publication number: 20160333488Abstract: Provided are an anode for an ion exchange membrane electrolyzer which enables an aqueous solution of an alkali metal chloride to be electrolyzed at a lower voltage than a conventional anode and allows the concentration of an impurity gas included in an anode gas to be reduced and an ion exchange membrane electrolyzer using the same. The anode is an anode for an ion exchange membrane electrolyzer to be used in an ion exchange membrane electrolyzer that is separated by an ion exchange membrane into an anode chamber and a cathode chamber. The anode for an ion exchange membrane electrolyzer comprises at least one perforated flat metal plate 1 (expanded metal 1) and the thickness of the perforated flat metal plate 1 (expanded metal 1) ranges from 0.1 to 0.5 mm and the ratio of the short way SW to the long way LW (SW/LW) ranges from 0.45 to 0.55. The short way SW is preferably not more than 3.0 mm.Type: ApplicationFiled: January 15, 2015Publication date: November 17, 2016Applicants: THYSSENKRUPP UHDE CHLORINE ENGINEERS (JAPAN) LTD., TOSOH CORPORATIONInventors: Terumi HASHIMOTO, Koji KAWANISHI, Fumio SADAHIRO, Shota SHINOHARA, Sachio KANEKO
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Publication number: 20150365740Abstract: A transmission apparatus includes: a plurality of first devices; and a second device configured to output a data signal shared by the plurality of first devices and respective first clock signals to each of the plurality of first devices, and to control the plurality of first devices individually based on the respective first clock signals.Type: ApplicationFiled: April 2, 2015Publication date: December 17, 2015Applicant: FUJITSU LIMITEDInventor: Shota Shinohara
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Patent number: 9167320Abstract: A transmission method for transmitting a lower-speed signal transmission frame using a node device in a network by accommodating the lower-speed signal transmission frame into time slots of a higher-speed signal transmission frame includes supplying, when a number of the time slots accommodating the lower-speed signal transmission frame is to be increased, the time slots to input numbers of a cross-connection part of the node device in accordance with an order of time slot numbers of the time slots; and re-establishing cross-connections where the input numbers are cross-connected to corresponding output numbers of the cross-connection part so that the cross-connections are prevented from crossing each other, wherein the input numbers input the time slots and the output numbers output the time slots.Type: GrantFiled: March 20, 2013Date of Patent: October 20, 2015Assignee: FUJITSU LIMITEDInventors: Shota Shinohara, Wataru Odashima, Hiroyuki Homma, Junichi Sugiyama
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Publication number: 20150132012Abstract: A transmission apparatus includes: a plurality of logical lanes; a receiver configured to receive a signal including synchronization information of a frame; a distributor configured to divide data included in the received signal into frame elements and cause the plurality of logical lanes to store the data; and a transmitter configured to transmit the data stored in the logical lanes to lines corresponding to the logical lanes. When the data is stored in the plurality of logical lanes, the distributor groups the logical lanes into a plurality of groups and associates the frame elements with the synchronization information.Type: ApplicationFiled: January 12, 2015Publication date: May 14, 2015Inventors: Hayato Furukawa, Wataru Odashima, Shota Shinohara, Toru Katagiri
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Patent number: 8891667Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.Type: GrantFiled: March 7, 2013Date of Patent: November 18, 2014Assignee: Fujitsu LimitedInventors: Junichi Sugiyama, Makoto Shimizu, Wataru Odashima, Shota Shinohara, Hiroyuki Homma
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Publication number: 20140119733Abstract: There is provided a frame converter that writes input data included in an input frame to a buffer to accumulate the input data and outputs data read from the buffer as output data included in an output frame, the frame converter includes a setting unit configured to set a time interval from start of resizing of data rate of the input data to start of resizing of data rate of the output data when resizing of an accumulation amount in the buffer is performed in which data rates of the input data and the output data vary, and an adjustment unit configured to adjust to approximate the data rate of the output data to the data rate of the input data after the time interval has elapsed since the start of resizing of data rate of the input data.Type: ApplicationFiled: September 10, 2013Publication date: May 1, 2014Applicant: FUJITSU LIMITEDInventors: Makoto Shimizu, Shota Shinohara
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Publication number: 20130259484Abstract: A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots.Type: ApplicationFiled: March 1, 2013Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Hidetaka KAWAHARA, Junichi SUGIYAMA, Wataru ODASHIMA, Shota SHINOHARA, Hiroyuki HOMMA
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Publication number: 20130259476Abstract: A transmission method for transmitting a lower-speed signal transmission frame using a node device in a network by accommodating the lower-speed signal transmission frame into time slots of a higher-speed signal transmission frame includes supplying, when a number of the time slots accommodating the lower-speed signal transmission frame is to be increased, the time slots to input numbers of a cross-connection part of the node device in accordance with an order of time slot numbers of the time slots; and re-establishing cross-connections where the input numbers are cross-connected to corresponding output numbers of the cross-connection part so that the cross-connections are prevented from crossing each other, wherein the input numbers input the time slots and the output numbers output the time slots.Type: ApplicationFiled: March 20, 2013Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Shota SHINOHARA, Wataru Odashima, Hiroyuki Homma, Junichi Sugiyama
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Publication number: 20130243114Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.Type: ApplicationFiled: March 7, 2013Publication date: September 19, 2013Applicant: FUJITSU LIMITEDInventors: Junichi SUGIYAMA, Makoto SHIMIZU, Wataru ODASHIMA, Shota SHINOHARA, Hiroyuki HOMMA