Abstract: A liquid crystal display device includes a display panel having a plurality of pixels that is defined by a plurality of gate lines and a plurality of source lines and is each provided with a switching element and a pixel electrode. The liquid crystal display device further includes a gate line drive circuit configured to scan the gate lines, and a source line drive circuit configured to supply each of the source lines with a data signal by means of column inversion driving. The gate line drive circuit divides the plurality of gate lines into at least two groups, and sequentially scans the gate lines once per group in one frame. The at least two groups include a group of the gate lines scanned in the one frame in a first direction in which the gate lines are aligned, and a group of the gate lines scanned in a second direction opposite to the first direction.

Abstract: To reduce manufacturing costs and facilitate analysis of the conditions of occurrence of an accident, a drive recorder includes a vehicle state detector (20, 30, 40) configured to detect a state of a vehicle, an imager (50) configured to capture images of surroundings of the vehicle, a storage controller (10) configured to control storage operation to store vehicle state data corresponding to the state of the vehicle and captured image data corresponding to the images captured by the imager, a display device (80) configured to carry out displaying based on display image data input to the display device, in which the display device (80) includes a nonvolatile memory (85) configured to store initial-setting data for controlling display operation, and the storage controller (10) causes the nonvolatile memory (85) of the display device (80) to store the captured image data of the images captured by the imager (50).

Abstract: A scan signal line driving circuit of at least one embodiment includes a plurality of stages which are aligned in a scanning direction, the scan signal line driving circuit receiving a first clock signal, a second clock signal, and a third clock signal, the first clock signal, the second clock signal, and the third clock signal being such that (i) a clock pulse of the third clock signal is followed by a clock pulse of the first clock signal, (ii) the clock pulse of the first clock signal is followed by a clock pulse of the second clock signal, and (iii) the clock pulse of the second clock signal is followed by the clock pulse of the third clock signal, the scan signal line driving circuit receiving a shift pulse at one endmost stage thereof and shifting the shift pulse from the one endmost stage thereof to the other endmost stage thereof stage by stage in accordance with each of clock pulses of the first clock signal, the second clock signal, and the third clock signal, sequentially received by the scan signa