Patents by Inventor Shotaro Umebachi

Shotaro Umebachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5196370
    Abstract: This invention relates to a method of manufacturing an Arsenic-including compound semiconductor device comprising the steps of forming an ion implantation layer in a specified region of an As compound semiconductor wafer, forming an As layer on the surface of the wafer, and annealing the water. In this manner, As evaporation in the ion implantation layer by annealing heat may be prevented. Accordingly, sufficient substitution of the implanted ions and the ions other than As ions composing the As compound may be achieved, thereby preventing lowering of the electrical activation of the As compound semiconductor device. In addition, the electrical activation becomes uniform over the whole area of the water.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: March 23, 1993
    Assignee: Matsushita Electronics Corporation
    Inventors: Katsushi Tara, Toshiharu Tambo, Kaname Motoyoshi, Hidetaka Hashimoto, Shotaro Umebachi, Susumu Koike
  • Patent number: 4351099
    Abstract: A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:forming on a silicon epitaxial layer (13) of n-type conductivity a doped oxide film (14) containing boron as an impurity to give p-type conductivity,forming a mask (15a, 16a) containing Si.sub.3 N.sub.
    Type: Grant
    Filed: May 12, 1980
    Date of Patent: September 28, 1982
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiromitsu Takagi, Shotaro Umebachi, Gota Kano, Iwao Teramoto
  • Patent number: 4075652
    Abstract: The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga.sub.1-y Al.sub.y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.
    Type: Grant
    Filed: May 5, 1977
    Date of Patent: February 21, 1978
    Assignee: Matsushita Electronics Corporation
    Inventors: Shotaro Umebachi, Gota Kano, Morio Inoue