Patents by Inventor Shou-Cheng Hu
Shou-Cheng Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113080Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 11855045Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: January 3, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 11387171Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.Type: GrantFiled: June 4, 2018Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Shou-Cheng Hu, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu, Chen-Shien Chen
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Publication number: 20220122944Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 11217562Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: December 16, 2019Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Publication number: 20210287966Abstract: A semiconductor package includes a substrate. The semiconductor package further includes a plurality of metal pillars on a top surface of the substrate. The semiconductor package further includes a semiconductor component on the substrate, wherein the semiconductor component includes one or more dies, and the semiconductor component has a top surface. The semiconductor package further includes a mold compound encapsulating the plurality of metal pillars and the semiconductor component, wherein the mold compound has a top surface above the top surface of the semiconductor component. The semiconductor package further includes an interposer coupled to the plurality of metal pillars.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventors: Hui-Min HUANG, Chen-Shien CHEN, Chung-Shi LIU, Chih-Wei LIN, Ming-Da CHENG, Shou-Cheng HU
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Patent number: 10854577Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.Type: GrantFiled: December 17, 2018Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Shien Chen, Shou-Cheng Hu
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Publication number: 20200118978Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 10510727Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: June 25, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Publication number: 20190123028Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Inventors: Chen-Hua Yu, Chen-Shien Chen, Shou-Cheng Hu
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Publication number: 20180308824Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 10008479Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: January 9, 2017Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 9837289Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.Type: GrantFiled: April 14, 2016Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shou-Cheng Hu, Ching-Wen Hsiao, Chen-Shien Chen
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Publication number: 20170125386Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: January 9, 2017Publication date: May 4, 2017Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 9543278Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: October 19, 2015Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Publication number: 20160284654Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Inventors: Chen-Hua Yu, Shou-Cheng Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
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Publication number: 20160233113Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.Type: ApplicationFiled: April 14, 2016Publication date: August 11, 2016Inventors: Shou-Cheng Hu, Ching-Wen Hsiao, Chen-Shien Chen
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Patent number: 9330947Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs.Type: GrantFiled: July 30, 2014Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shou-Cheng Hu, Ching-Wen Hsiao, Chen-Shien Chen
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Publication number: 20160111398Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: ApplicationFiled: October 19, 2015Publication date: April 21, 2016Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
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Patent number: 9293449Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.Type: GrantFiled: November 18, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shou-Cheng Hu, Chen-Shien Chen, Tin-Hao Kuo, Chih-Hua Chen, Ching-Wen Hsiao