Patents by Inventor Shou-Chi Tsai

Shou-Chi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186396
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first work function layer, a second work function layer, a protective layer, a gate stack, a first liner, a second liner, a planarization layer, and a gate plug. The first work function layer is disposed on a substrate. The second work function layer is disposed on the first work function layer. The protective layer is disposed on the second work function layer. The gate stack is disposed on the protective layer. The first liner is disposed on the gate stack. The second liner is disposed on the first liner. The planarization layer is disposed on the second liner. The gate plug is disposed on the planarization layer and in contact with the first work function layer and the second work function layer.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 6, 2024
    Inventors: Shou-Chi TSAI, Kai JEN
  • Patent number: 11690217
    Abstract: Provided is a dynamic random access memory including a substrate, a gate dielectric layer, a metal filling layer, an adhesion layer, multiple work function layers, and multiple doped regions. The substrate has a trench. The gate dielectric layer is located on a sidewall and a bottom surface of the trench. The metal filling layer is located in the trench. The adhesion layer is located between the gate dielectric layer and the metal filling layer. The work function layers are located in the trench, where each work function layer is located between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer. The doped regions are located in the substrate on both sides of the trench, where part of the work function layers and part of the gate dielectric layer are laterally sandwiched between part of the doped regions and part of the adhesion layer.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: June 27, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Shou-Chi Tsai, Chun-Lin Li
  • Publication number: 20230009397
    Abstract: Provided is a dynamic random access memory including a substrate, a gate dielectric layer, a metal filling layer, an adhesion layer, multiple work function layers, and multiple doped regions. The substrate has a trench. The gate dielectric layer is located on a sidewall and a bottom surface of the trench. The metal filling layer is located in the trench. The adhesion layer is located between the gate dielectric layer and the metal filling layer. The work function layers are located in the trench, where each work function layer is located between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer. The doped regions are located in the substrate on both sides of the trench, where part of the work function layers and part of the gate dielectric layer are laterally sandwiched between part of the doped regions and part of the adhesion layer.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 12, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Shou-Chi Tsai, Chun-Lin Li