Patents by Inventor Shou Ping Hsu

Shou Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7650255
    Abstract: A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204).
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: January 19, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Chi Tsung Lee, Sheng Pin Chen, Ming Chuan You, Shou Ping Hsu
  • Publication number: 20090276175
    Abstract: A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204).
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: Chi Tsung Lee, Sheng Pin Chen, Ming Chuan You, Shou Ping Hsu
  • Patent number: 7262619
    Abstract: An apparatus for mitigating condensation formation on a device interface board during low-temperature semiconductor device testing includes a nozzle. The nozzle includes an input orifice for receiving gas from a gas source and at least one output orifice for discharging gas from the nozzle against a surface of the device interface board. The area of the at least one output orifice is substantially greater than the area of input orifice.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Nai Liang Peng, Shou Ping Hsu