Patents by Inventor Shou-Po Shih

Shou-Po Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fully differential continuous-time current-mode high speed CMOS comparator
    Patent number: 6535029
    Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: March 18, 2003
    Assignee: Silicon Image, Inc.
    Inventors: Shou-Po Shih, Chieh-Yuan Chao, Yuming Cao, Yu-Jen Wu
  • Fully differential continuous-time current-mode high speed CMOS comparator
    Publication number: 20020186052
    Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.
    Type: Application
    Filed: May 1, 2001
    Publication date: December 12, 2002
    Inventors: Shou-Po Shih, Chieh-Yuan Chao, Yuming Cao, Yu-Jen Wu