Abstract: A method for forming a DRAM includes forming a bit line contact over the active area, forming a bit line over the bit line contact, and forming a hard mask layer over the bit line. The method includes forming a semiconductor material layer over the active area and forming a metal layer over the semiconductor material layer and the hard mask layer. The method includes removing the metal layer over the hard mask layer and exposing the top surface of the hard mask layer, and the remaining portion of the metal layer is between hard mask layers. The method includes removing a portion of the hard mask layer after exposing a portion of the hard mask layer. The method includes forming a capacitor contact conductive layer over the remaining portion of the metal layer after removing the portion of the hard mask layer.

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.

Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.