Abstract: The instant invention relates to an apparatus and method for enhancing DC offset correction speed of a radio device. On the exemplary, the apparatus includes one or two-stage signal-processing units and a controller. Each signal-processing unit has a baseband filter, a gain stage and a DC offset correction (DCOC) loop applied on the gain stage. A connection direction of an electrode terminal of a capacitor of the baseband filter is capable of being switched by the controller to process a pre-charge or a discharge phases thereby adjusting a bandwidth of the baseband filter to be either a normal operational bandwidth or wider than the normal operational bandwidth for rapidly setting time of the baseband filter.

Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

Abstract: The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

Abstract: A capacitor circuit includes a first capacitor having a positive terminal coupled to a first node and a negative terminal coupled to a second node, a second capacitor having a negative terminal coupled to the first node and a positive terminal coupled to the second node, a third capacitor having a positive terminal coupled to the first node and a negative terminal coupled to a third node, a fourth capacitor having a negative terminal coupled to the first node, and a positive terminal coupled to the third node, a first voltage drop generator coupled between the second node and a fourth node for providing a first voltage drop between the second node and the fourth node, and a second voltage drop generator coupled between the fourth node and the third node for providing a second voltage drop between the fourth node and the third node.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: An input/output device comprises a bonding pad, a signal transport circuit, and a blocking unit. The signal transport circuit has a first terminal connected to the bonding pad and a second terminal connected to a core circuit of an IC product. The signal transport circuit is capable of transporting a signal either from the bonding pad to the core circuit or from the core circuit to the bonding pad. The blocking unit has a control terminal and is coupled between the bonding pad and the signal transport circuit. The control terminal is coupled to receive an enable signal. The blocking unit ties the bonding pad to a predetermined voltage level when the enable signal is de-asserted, thereby blocking the signal transport provided by the signal transport circuit. The blocking unit unties the bonding pad from the predetermined voltage level when the enable signal is asserted.

Abstract: The instant invention relates to an apparatus and method for enhancing DC offset correction speed of a radio device. On the exemplary, the apparatus includes one or two-stage signal-processing units and a controller. Each signal-processing unit has a baseband filter, a gain stage and a DC offset correction (DCOC) loop applied on the gain stage. A connection direction of an electrode terminal of a capacitor of the baseband filter is capable of being switched by the controller to process a pre-charge or a discharge phases thereby adjusting a bandwidth of the baseband filter to be either a normal operational bandwidth or wider than the normal operational bandwidth for rapidly setting time of the baseband filter.

Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.

Abstract: Calibration methods and circuits for suppressing second order distortion in a direct conversion receiver. In the calibration method, a signal output by a down converter is filtered to obtain an interference signal, and strength of the interference signal is detected. A calibration code is obtained according to the detected strength of the interference signal, and the down converter is adapted according to the calibration code to suppress second order distortion.

Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.

Abstract: An analog demodulator used in a low IF receiver to down-convert a pair of quadratureIF signals and to perform image-rejection operations. The analog demodulator includes at least one first calibration apparatus and/or at least one second calibration apparatus so that the analog demodulator can reduce DC offset that would cause LO leakage in the low IF receiver by using the first calibration apparatus and/or the second calibration apparatus. The analog demodulator further includes a filtering device connected to a LO generator for removing the 3rd and 5th order harmonic components.

Abstract: A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.