Patents by Inventor Shou-Wan Huang

Shou-Wan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420564
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Patent number: 11791412
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: October 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Publication number: 20220262687
    Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Publication number: 20220223728
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Publication number: 20220181481
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure; and forming a first gate structure and a second gate structure on the DDB structure. Preferably, a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure.
    Type: Application
    Filed: January 4, 2021
    Publication date: June 9, 2022
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Patent number: 11355639
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure; and forming a first gate structure and a second gate structure on the DDB structure. Preferably, a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Patent number: 8927058
    Abstract: A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Shou-Wan Huang, Kuan-Hua Su
  • Publication number: 20100003403
    Abstract: A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Kuan-Hua Su
  • Publication number: 20050196951
    Abstract: A method of forming at least one wire on a substrate comprising at least one conductive region is provided. AnAn insulatingayer is disposed on the substrate. The method includes forming a hard mask layer on the insulating layer followed by forming at least one recess by removing portions of the hard mask layer and the insulating layer, forming a light blocking layer on the hard mask layer and the recess, and the light blocking layer and the hard mask layer forming a composite layer, forming a gap filling layer filling up the recess on the light blocking layer, forming a photoresist layer on the gap filling layer, aligning a photo mask with the recess by utilizing the composite layer as a mask, and performing an exposure/development process to form at least one pattern above the recess in the photoresist layer.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 8, 2005
    Inventors: Benjamin Szu-Min Lin, Shou-Wan Huang