Patents by Inventor Shou Yen Chou

Shou Yen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9448470
    Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Shou-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen
  • Publication number: 20140365982
    Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Inventors: Ru-Gun Liu, Shou-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen
  • Publication number: 20130293858
    Abstract: The present disclosure provides a photomask. The photomask includes a substrate. The photomask also includes a plurality of patterns disposed on the substrate. Each pattern is phase shifted from adjacent patterns by different amounts in different directions. The present disclosure also includes a method for performing a lithography process. The method includes forming a patternable layer over a wafer. The method also includes performing an exposure process to the patternable layer. The exposure process is performed at least in part through a phase shifted photomask. The phase shifted photomask contains a plurality of patterns that are each phase shifted from adjacent patterns by different amounts in different directions. The method includes patterning the patternable layer.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Burn Jeng Lin, Hoi-Tou Ng, Ken-Hsien Hsieh, Shou-Yen Chou
  • Patent number: 7266803
    Abstract: Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou Yen Chou, Jaw Jung Shin, Tsai Sheng Gau, Burn Jeng Lin
  • Publication number: 20070028206
    Abstract: Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou-Yen Chou, Jaw-Jung Shin, Tsai-Sheng Gau, Burn Lin