Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.