Abstract: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode.

Abstract: A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, a method starts by forming a host dielectric layer over a first and second region of a substrate. A first dielectric capping layer is formed overlying the host dielectric layer on the first and second region and later selectively removed to expose an underlying layer on the first region. A Hf-based dielectric capping layer is formed overlying the underlying layer on the first region and the first dielectric capping layer on the second region. The Hf-based dielectric capping layer is selected to have a healing effect on the exposed surface of the underlying layer on the first region. A control electrode is formed overlaying the Hf-based dielectric capping layer on the first region and on the second region.

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Abstract: A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method relates to providing a substrate with a first and a second region. A gate dielectric is formed overlying the first and the second region. A metal gate layer is formed overlying the gate dielectric on the first and the second region. The metal gate layer has a first (as-deposited) work function that can be modified upon inducing strain thereon. The method further relates to selecting a first strain which induces a first pre-determined work function shift (?WF1) in the first (as-deposited) work function of the metal gate layer on the first region and selectively forming a first strained conductive layer overlying the metal gate layer on the first region, the first strained conductive layer exerting the selected first strain on the metal gate layer.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously.

Abstract: The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region.

Abstract: A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function and a work function modulating element (6) for modulating the work function of the material of the main electrode (4) towards a predetermined value. The main electrode (4) furthermore comprises a diffusion preventing dopant element (5) for preventing diffusion of the work function modulating element (6) towards and/or into the dielectric (3). Methods for forming such a semiconductor device are also described.

Abstract: A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric which is in direct contact with the fully silicided electrode comprises a stopping material for substantially preventing the workfunction modulating element from implantation into and/or diffusing towards the dielectric. A method for forming such a semiconductor device is also disclosed.

Abstract: A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.

Abstract: A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.

Abstract: The present invention provides a method for fabricating elevated and drain structures on a substrate. A first insulating layer is formed over a silicon substrate. A first barrier layer is formed over the first insulating layer. The first barrier layer, the first insulating layer and the substrate are patterned to form a trench. Ions are implanted into the substrate in the trench. A gate oxide layer is formed on the substrate in the trench. A polysilicon layer is deposited over the gate oxide layer and the barrier layer. The polysilicon layer is planarized using a chemical mechanical polishing process (CMP) stopping on the barrier layer to form a novel recessed gate. The barrier layer and the first insulating layer are removed. Lightly doped source/drain regions (LDD) are formed adjacent to the recessed gate. Spacers are formed on the sidewalls of the recessed gate. Source and drain regions are formed adjacent to the spacers.

Abstract: A titanium based SALICIDE process that is free of bridging effects is described. A controlled quantity of nitrogen is delivered to the silicon oxide (or nitride) surface during titanium silicide formation. The amount of nitrogen is sufficient to inhibit outdiffusion of silicon at the dielectric areas, but insufficient to affect the sheet resistance of the silicon areas. This is accomplished by means of a titanium/titanium-rich titanium nitride/titanium sandwich that is formed in a single sputtering operation. An optional cap layer of stoichiometric titanium nitride may also be added.

Abstract: A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted.

Abstract: A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both germanium and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is particularly beneficial in the manufacture of sub-micron CMOS integrated circuits. Germanium is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates a balanced formation of titanium suicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices with an accompanying reduction of gate-to-source/drain shorts. Amorphization by the electrically neutral germanium ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted.