Abstract: A switching converter and a low-voltage startup circuit is provided. The low-voltage startup circuit includes a comparator and a substrate voltage control module. The comparator performs a comparison between an input voltage and a reference voltage and obtain a voltage detection signal according to a result of the comparison. The substrate voltage control module adjusts a substrate voltage of a main switching transistor according to the voltage detection signal, wherein when the voltage detection signal indicates that the input voltage is lower than/equal to the reference voltage, the substrate voltage control module increases the substrate voltage of the main switching transistor, and then a turn-on threshold voltage of the main switching transistor can be reduced, so that the main switching transistor may be normally turned on when the input voltage is low, and the low-voltage startup capability of the switching converter is improved.

Abstract: A switching converter and a low-voltage startup circuit is provided. The low-voltage startup circuit includes a comparator and a substrate voltage control module. The comparator performs a comparison between an input voltage and a reference voltage and obtain a voltage detection signal according to a result of the comparison. The substrate voltage control module adjusts a substrate voltage of a main switching transistor according to the voltage detection signal, wherein when the voltage detection signal indicates that the input voltage is lower than/equal to the reference voltage, the substrate voltage control module increases the substrate voltage of the main switching transistor, and then a turn-on threshold voltage of the main switching transistor can be reduced, so that the main switching transistor may be normally turned on when the input voltage is low, and the low-voltage startup capability of the switching converter is improved.

Abstract: Disclosed is a switching power supply circuit and a control circuit and a control method thereof. The control circuit comprises a control unit and a driving unit. The control unit controls the driving unit to provide a driving signal with different driving strengths according to a comparison result between a switching voltage and a preset voltage, so as to adjust a speed of turning the power switch off. By controlling the driving strength of the driving signal, a rising rate of the switching voltage can be improved, a spike of the switching voltage can be reduced, various components in the circuit can be protected from being damaged by the spike, and service life and reliability of the circuit can be improved.

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin+?Vin?) to a maximum voltage selector circuit (53) that produces an internal voltage (VRAIL-TOP) equal to the larger of a first supply voltage (VREG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin+?Vin?) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal, (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN)

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).