Patents by Inventor Shouhei Yamamoto

Shouhei Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299769
    Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventor: SHOUHEI YAMAMOTO
  • Patent number: 11695415
    Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 4, 2023
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Shouhei Yamamoto
  • Publication number: 20220209769
    Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 30, 2022
    Inventor: SHOUHEI YAMAMOTO
  • Patent number: 6246288
    Abstract: In order to reduce power consumption and prevent crossover distortion, the difference between a negative phase input voltage and a positive phase input voltage is amplified at a differential stage and a differential output voltage is output. The state of continuity of an NMOS transistor is controlled with the differential output voltage. By controlling the product of the current flowing through a resistor and the resistance value of this resistor, the level shift voltage at a level shift stage can be controlled. The level of the differential output voltage is shifted by using the level shift voltage, a level shift output voltage is output from the level shift stage and the state of continuity of another NMOS transistor is controlled. The state of continuity of a PMOS transistor is controlled with the differential output voltage, and an amplified voltage is output through an output terminal.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: June 12, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shouhei Yamamoto