Patents by Inventor Shouichi Kobayashi

Shouichi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8866284
    Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Shouichi Kobayashi, Hiroaki Suzuki, Kazuhide Uriu, Koichi Seko, Takashi Yui, Kiyomi Hagihara
  • Patent number: 8659138
    Abstract: A semiconductor package includes a substrate, a semiconductor chip disposed on the substrate, and a connection wiring connected electrically to the semiconductor chip. The semiconductor package further includes a sidewall formed of an insulator, an inner electrode formed on a first surface of the sidewall that faces the substrate, and a sidewall external electrode formed on a second surface of the sidewall different from the first surface. The inner electrode and the sidewall external electrode are connected electrically, and the inner electrode is connected to the connection wiring. With this configuration, it is possible to suppress the semiconductor package from being large due to an increase in the number of sidewall external electrodes formed on the side surfaces of the semiconductor package, and to shorten a connection distance between the semiconductor packages by connecting the sidewall external electrodes.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Shouichi Kobayashi, Hiroyuki Tanaka
  • Publication number: 20130299957
    Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.
    Type: Application
    Filed: July 10, 2013
    Publication date: November 14, 2013
    Inventors: SHOUICHI KOBAYASHI, HIROAKI SUZUKI, KAZUHIDE URIU, KOICHI SEKO, TAKASHI YUI, KIYOMI HAGIHARA
  • Publication number: 20120326293
    Abstract: A semiconductor package includes a substrate, a semiconductor chip disposed on the substrate, and a connection wiring connected electrically to the semiconductor chip. The semiconductor package further includes a sidewall formed of an insulator, an inner electrode formed on a first surface of the sidewall that faces the substrate, and a sidewall external electrode formed on a second surface of the sidewall different from the first surface. The inner electrode and the sidewall external electrode are connected electrically, and the inner electrode is connected to the connection wiring. With this configuration, it is possible to suppress the semiconductor package from being large due to an increase in the number of sidewall external electrodes formed on the side surfaces of the semiconductor package, and to shorten a connection distance between the semiconductor packages by connecting the sidewall external electrodes.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Shouichi KOBAYASHI, Hiroyuki TANAKA
  • Patent number: 6897097
    Abstract: The semiconductor device comprises: a tub for supporting a semiconductor chip; a sealing body formed by sealing the semiconductor chip with a resin; a plurality of leads made of a copper alloy, exposed to the back face of the sealing body, and having a soldered layer on the exposed mounted face; and wires for connecting the pads of the semiconductor chip and the corresponding leads. In the manufacture method, the sealing body is polished, after resin-molded, at its back face with a brush to form the two widthwise edge portions, as exposed from the back face of the sealing body, of the lead into rounded faces, and the mounted face of the lead including the rounded faces is protruded at its central portion from the back face of the sealing body thereby to improve the connection reliability at the packaging time.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: May 24, 2005
    Assignees: Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Patent number: 6885850
    Abstract: A transmission power control apparatus for outputting a transmission data to be filtered by a band-limiting filter (9), includes: a branching unit (81) for branching transmission data before being entered into the band-limiting filter (9); a peak detecting filter (84) having the same structure as that of the band-limiting filter (9), for entering thereinto one of the transmission data branched by this branching unit (81); units (85 to 89) for calculating a correction value capable of suppressing a power peak of the transmission data by being filtered by this peak detecting filter (84); a delaying unit for delaying the other data of the branched transmission data by time required to calculate the correction value; and a correcting unit (83) for correcting the transmission data delayed by this delaying unit (82) based upon the correction value, and thereafter, for entering the corrected transmission data into the band-limiting filter (9).
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: April 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shouichi Kobayashi, Hiroki Shinde
  • Patent number: 6819721
    Abstract: A limiting method is provided which limits signals having two components I channel and Q channel on two orthogonal coordinate axes within a predetermined range on the coordinate plane specified by the two coordinate axes, wherein the predetermined range is defined by concentric circles having the origin of the two coordinate axes as a center.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: November 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shouichi Kobayashi, Hiroki Shinde
  • Publication number: 20040058479
    Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method.
    Type: Application
    Filed: September 25, 2003
    Publication date: March 25, 2004
    Applicants: Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Patent number: 6667193
    Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method. The semiconductor device comprises: a tub 1e for supporting a semiconductor chip 2; a sealing body 3 formed by sealing the semiconductor chip 2 with a resin; a plurality of leads 1a made of a copper alloy, exposed to the back face 3a of the sealing body 3, and having a soldered layer 8 on the exposed mounted face 1d; and wires 4 for connecting the pads 2a of the semiconductor chip 2 and the corresponding leads 1a.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: December 23, 2003
    Assignees: Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Patent number: 6590276
    Abstract: The semiconductor device comprises: a tub for supporting a semiconductor chip; a sealing body formed by sealing the semiconductor chip with a resin; a plurality of leads made of a copper alloy, exposed to the back face of the sealing body, and having a soldered layer on the exposed mounted face; and wires for connecting the pads of the semiconductor chip and the corresponding leads. In the manufacture method, the sealing body is polished, after resin-molded, at its back face with a brush to form the two widthwise edge portions, as exposed from the back face of the sealing body, of the lead into rounded faces, and the mounted face of the lead including the rounded faces is protruded at its central portion from the back face of the sealing body thereby to improve the connection reliability at the packaging time.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: July 8, 2003
    Assignees: Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Publication number: 20020106836
    Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method.
    Type: Application
    Filed: March 29, 2002
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Publication number: 20020102771
    Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method.
    Type: Application
    Filed: March 29, 2002
    Publication date: August 1, 2002
    Applicant: Hitachi, Ltd. and Hitachi Yonezawa Electronics Co. , Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Patent number: 6399423
    Abstract: The semiconductor device comprises: a tub for supporting a semiconductor chip; a sealing body formed by sealing the semiconductor chip with a resin; a plurality of leads made of a copper alloy, exposed to the back face of the sealing body, and having a soldered layer on the exposed mounted face; and wires for connecting the pads of the semiconductor chip and the corresponding leads. In the manufacture method, the sealing body is polished, after resin-molded, at its back face with a brush to form the two widthwise edge portions, as exposed from the back face of the sealing body, of the lead into rounded faces, and the mounted face of the lead including the rounded faces is protruded at its central portion from the back face of the sealing body thereby to improve the connection reliability at the packaging time.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: June 4, 2002
    Assignees: Hitachi, Ltd, Hitachi Yonezawa Electronics Co., Ltd.
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya
  • Publication number: 20020065095
    Abstract: A transmission power control apparatus for outputting a transmission data to be filtered by a band-limiting filter (9), includes: a branching unit (81) for branching transmission data before being entered into the band-limiting filter (9); a peak detecting filter (84) having the same structure as that of the band-limiting filter (9), for entering thereinto one of the transmission data branched by this branching unit (81); units (85 to 89) for calculating a correction value capable of suppressing a power peak of the transmission data by being filtered by this peak detecting filter (84); a delaying unit for delaying the other data of the branched transmission data by time required to calculate the correction value; and a correcting unit (83) for correcting the transmission data delayed by this delaying unit (82) based upon the correction value, and thereafter, for entering the corrected transmission data into the band-limiting filter (9).
    Type: Application
    Filed: November 6, 2001
    Publication date: May 30, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shouichi Kobayashi, Hiroki Shinde
  • Publication number: 20010041424
    Abstract: To improve the connection reliability at the time of packaging a semiconductor device and to make the method management easy in a semiconductor device manufacturing method.
    Type: Application
    Filed: December 12, 2000
    Publication date: November 15, 2001
    Inventors: Takao Matsuura, Yoshihiko Yamaguchi, Shouichi Kobayashi, Kouji Tsuchiya