Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.

Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.

Abstract: A semiconductor storage device in an embodiment includes a memory cell array, a pad to which data is inputted, an ODT circuit connected to the pad, an ODT driver configured to drive the ODT circuit, and a control circuit configured to supply an enable signal and a resistance value control signal to the ODT driver. The pad is arranged between the memory cell array and a first end side of the semiconductor storage device, and the ODT circuit is arranged between the pad and the first end side. The ODT driver is arranged between the ODT circuit and the first end side. An ODT control signal line configured to transmit a resistance value control signal, and an ODT enable signal line configured to transmit an enable signal are arranged between the ODT driver and the first end side.

Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

Abstract: According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer.

Abstract: According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer.

Abstract: According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.

Abstract: According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory.

Abstract: According to one embodiment, a ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.