Patents by Inventor Shouichirou Yamada

Shouichirou Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5329474
    Abstract: In a Fast Fourier Transform method, the elements of Fast Fourier Transform are arranged as a two-dimensional square and stored in areas of an array whose number of lines is twice that of columns. Positions of the columns having bit reversed column numbers are exchanged and the elements are linear vector stored so that the initial element of a column is always one position lower than the previous one. Then, the elements of such linear vector stored array are rearranged through exchange of columns having elements with bit reversed numbers and movement of the columns fully upward to made them flush.
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: July 12, 1994
    Assignee: NEC Corporation
    Inventor: Shouichirou Yamada
  • Patent number: 5327367
    Abstract: A computer system for Fast Fourier Transform provided with a vector functional unit with a process to store rotation factors. The input elements are multiplied in Fast Fourier Transform into an array. When the number of the rotation factors with the same value is not less than the maximum number of vector elements for the vector functional unit, the rotation factor with the same value is stored only once each time the vector elements amounts to the maximum number.
    Type: Grant
    Filed: December 7, 1992
    Date of Patent: July 5, 1994
    Assignee: NEC Corporation
    Inventor: Shouichirou Yamada
  • Patent number: 5287509
    Abstract: A system for multitasking inner loops, such as DO loops, using multiprocessors, provided with a plurality of shared registers each corresponding to one of a plurality of individual processors comprising the multiprocessor system. The plurality of shared registers store start and end values of segments resulting from dividing ranges of loop variables corresponding to the inner loops. The system for multitasking inner loops comprises an executing unit for iteratively executing the processing of the inner loops until the end value is reached. The system also comprises a decision unit for deciding whether or not there remain any unprocessed loops. Finally, the system comprises a continuing unit, responsive to the decision unit for continuing processing of the unprocessed loop or loops by transferring a part of a range which the loop variables corresponding to the unprocessed loop or loops can have.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: February 15, 1994
    Assignee: NEC Corporation
    Inventor: Shouichirou Yamada