Abstract: A semiconductor memory circuit according to the present invention comprises a decode circuit responsive to an internal address for generating a signal of a predetermined level, a drive circuit responsive to a word line activating signal for generating a word line selection signal corresponding to an output level of the decode circuit and a shutdown circuit responsive to a control signal for disconnecting the decode circuit from a ground terminal.With this construction, since the decode circuit is disconnected from the ground terminal during a time period for which a memory sense amplifier operates, an output level of the word line selection signal is not affected by noise even if the latter is generated on the ground line during that period. Therefore, it is possible to keep the memory cell in a stable selection state.

Abstract: A buffer circuit which can operate with reduced power consumption and at a high speed is disclosed. The buffer circuit is of the type having a flip-flop circuit with a pair of output terminals and a pair of boot-strap circuits each provided for each of the output terminals and having a capacitor and a precharge circuit for precharging the capacitor, and is featured in that a pair of control circuits are provided to the pair of boot-strap circuits. Each of the control circuits allows the capacitor to be charged when the associated output terminal is about to produce a high level signal and inhibits the capacitor from being charged when the associated output terminal is about to produce a low level signal.

Abstract: For perfect states of balance on sense nodes, there is provided a sense amplifier circuit comprising a balancing circuit capable of establishing an electrical path between not only the sense nodes but also the sense nodes and control nodes which are operable to control transistors provided between the sense nodes and a voltage supply to apply the supply voltage level to one of the sense nodes and remain low level on the other sense node for preparation of reading out of an accessed information. The current path simultaneously established on the beginning of precharging prevents the sense nodes from influence of the large differential voltage on the control nodes, thereby producing the perfect balance states on all the nodes and being conducive to precise judgement on the read out information.

Abstract: A memory circuit provided with improved noise-prevention circuit arrangement for word lines is disclosed. The memory circuit is structured in such a manner that each word decoder is provided for each word line group including a plurality of word lines for selecting the associated word line group, and a noise-prevention circuit of a flip flop type is provided for each of the work decoder for preventing an output of the word decoder from floating when that word decoder is not selected.