Abstract: Only once every N horizontal scanning periods, correction processing for providing a correction voltage for correcting a characteristic of a drive transistor for driving a light-emitting element formed in a display device to data lines of the display device and display driving processing for sequentially providing, to the data lines of the display device, gradation voltages for one horizontal scanning line based on a video signal corresponding to each of N horizontal scanning lines are executed.

Abstract: Only once every N horizontal scanning periods, correction processing for providing a correction voltage for correcting a characteristic of a drive transistor for driving a light-emitting element formed in a display device to data lines of the display device and display driving processing for sequentially providing, to the data lines of the display device, gradation voltages for one horizontal scanning line based on a video signal corresponding to each of N horizontal scanning lines are executed.

Abstract: Only once every N horizontal scanning periods, correction processing for providing a correction voltage for correcting a characteristic of a drive transistor for driving a light-emitting element formed in a display device to data lines of the display device and display driving processing for sequentially providing, to the data lines of the display device, gradation voltages for one horizontal scanning line based, on a video signal corresponding to each of N horizontal scanning lines are executed.

Abstract: Only once every N horizontal scanning periods, correction processing for providing a correction voltage for correcting a characteristic of a drive transistor for driving a light-emitting element formed in a display device to data lines of the display device and display driving processing for sequentially providing, to the data lines of the display device, gradation voltages for one horizontal scanning line based, on a video signal corresponding to each of N horizontal scanning lines are executed.

Abstract: First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing deselection are generated based on selection designation data. The first to N-th selection signals are individually latched, and first to N-th delayed selection signals are generated by individually delaying the first to N-th selection signals by a greater amount of delay when the latched selection signals transition from the first logic level to the second logic level than when the latched selection signals transition from the second logic level to the first logic level. A delayed data signal is selected corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals. The selected delayed data signal is output.

Abstract: First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing deselection are generated based on selection designation data. The first to N-th selection signals are individually latched, and first to N-th delayed selection signals are generated by individually delaying the first to N-th selection signals by a greater amount of delay when the latched selection signals transition from the first logic level to the second logic level than when the latched selection signals transition from the second logic level to the first logic level. A delayed data signal is selected corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals. The selected delayed data signal is output.

Abstract: A power-down circuit for an image display panel has a switch connected between a ground power line and a display power line, which carries a display voltage higher than the main power supply voltage of the device. When the main power supply voltage falls below a certain level, the control terminal of the switch is connected to the display power line through a voltage dropping element, thereby turning the switch on to discharge the display voltage to ground. The voltage dropping element, which may be a parasitic diode, ensures that the switch remains on until the display voltage has reached or nearly reached the ground level.

Abstract: When count values CNT of a counter 11 are values other than 1, a selection signal SEL of a decode section 18 becomes “H”, so that a clock signal CLK is selected by a selection section 17 and it is inputted into the counter 11 and a shift section 15 as a display clock signal DCK. When the count value CNT becomes 1, the selection signal SEL becomes “L”, so that a clock signal CLK divided into ½ by a division section 16 is selected in the selection section 17 and outputted as the display clock signal DCK. Thereby, the count value CNT is maintained to be 1 for two cycles of the clock signal CLK. Thereby, the pulse width of a common signal C1 outputted from the shift section 15 becomes two times the pulse width of the other common signals C2 to C33. Therefore, large pixels driven on the basis of the common signal C1 can be displayed with the same contrast.

Abstract: A power-down circuit for an image display panel has a switch connected between a ground power line and a display power line, which carries a display voltage higher than the main power supply voltage of the device. When the main power supply voltage falls below a certain level, the control terminal of the switch is connected to the display power line through a voltage dropping element, thereby turning the switch on to discharge the display voltage to ground. The voltage dropping element, which may be a parasitic diode, ensures that the switch remains on until the display voltage has reached or nearly reached the ground level.

Abstract: When count values CNT of a counter 11 are values other than 1, a selection signal SEL of a decode section 18 becomes “H”, so that a clock signal CLK is selected by a selection section 17 and it is inputted into the counter 11 and a shift section 15 as a display clock signal DCK. When the count value CNT becomes 1, the selection signal SEL becomes “L”, so that a clock signal CLK divided into ½ by a division section 16 is selected in the selection section 17 and outputted as the display clock signal DCK. Thereby, the count value CNT is maintained to be 1 for two cycles of the clock signal CLK. Thereby, the pulse width of a common signal C1 outputted from the shift section 15 becomes two times the pulse width of the other common signals C2 to C33. Therefore, large pixels driven on the basis of the common signal C1 can be displayed with the same contrast.

Abstract: A driving circuit includes a driving signal generating circuit which generates a plurality of driving signals; a plurality of switching circuits which are supplied with the driving signals so as to supply driving voltages in response to the driving signals, respectively; an output node which is connected to each of the switching circuits and is supplied with one of the driving voltages selectively; and a control circuit which controls the switching circuits so that any two of the switching circuits are not turned on simultaneously.

Abstract: A driving circuit includes a driving signal generating circuit which generates a plurality of driving signals (S12-S24); a plurality of switching circuits (31, 32, 35, 39) which are supplied with the driving signals (S21-S24) so as to supply driving voltages (V1-V4) in response to the driving signals (S21-S24), respectively; an output node (NO) which is connected to each of the switching circuits (31, 32, 35, 39) and is supplied with one of the driving voltages (V1-V4) selectively; and a control circuit which controls the switching circuits (31, 32, 35, 39) so that any two of the switching circuits (31, 32, 35, 39) are not turned on simultaneously.