Patents by Inventor Shouji Satou

Shouji Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6815322
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Publication number: 20040215513
    Abstract: It is possible to increase the click number for a banner advertisement without demanding irrational efforts to users. The present invention provides a server for transferring a banner advertisement to a plurality of clients connected thereto through a network, and the server comprises a means for analyzing a click signal for a banner advertisement, a means for counting the signal for each clients registered in the server, and a means for deciding a transfer amount of the banner advertisement relating to the registered client in response to the total count. The click signal analyzing means analyzes a clicked banner advertisement, a registered client having clicked, and a time point of clicking.
    Type: Application
    Filed: January 22, 2004
    Publication date: October 28, 2004
    Inventors: Tomonori Fujisawa, Shouji Satou
  • Publication number: 20040203925
    Abstract: The present invention provides local information indispensable for travelers or the like and serves as a guide satisfying the travelers' tastes at places where the travelers are staying on their journeys. Positional information is detected from an information request signal transmitted from a cellular terminal, and when the cellular terminal is within a specific area, information corresponding to the specific area is delivered to the cellular terminal in a form of a quiz or a game. Further to a response from the cellular terminal for the information delivered to the cellular terminal, a result record is delivered, and when the cellular terminal is not within the specific area, information other than that corresponding to the specific area is delivered. When giving a point according to the result, a point for the information corresponding to the specific area is set at a higher value as compared to that for the information other than that corresponding to the specific area.
    Type: Application
    Filed: February 23, 2004
    Publication date: October 14, 2004
    Inventors: Tomonori Fujisawa, Shouji Satou
  • Patent number: 6795346
    Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: September 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hidenari Otani, Kunihiko Suzuki, Shouji Satou
  • Publication number: 20040126747
    Abstract: The present invention provides an electronic mail communication method via a stuffed toy. At a mail center, a mail address for an owner of a stuffed toy is acquired together with ID code assigned to the stuffed toy, and data related to the ID code is transmitted as an electronic mail to the owner. The electronic mail is based on a conversational text including characters, signs, graphics, voices, or sounds, and the owner can enjoy communications with the stuffed toy by overlapping the images provided through the communications with an image of the stuffed toy at the owner's hand.
    Type: Application
    Filed: August 18, 2003
    Publication date: July 1, 2004
    Inventors: Tomonori Fujisawa, Shouji Satou
  • Publication number: 20040014283
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 22, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Publication number: 20030120612
    Abstract: An electronic settlement system with extremely high security based on the use of a mobile terminal with an electronic camera therein. Display units for commodity information provided at a place for payment with cash, a sales control server for managing the display units, a server for controlling the mobile terminals, and an authentication server authorizing the mobile terminals are connected to each other through the Internet, and the authentication server and the sales control server are connected to each other through a dedicated communication line.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 26, 2003
    Applicant: KABUSHIKI KAISHA EIGHTING
    Inventors: Tomonori Fujisawa, Shouji Satou
  • Publication number: 20030109096
    Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC) In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a nonvolatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.
    Type: Application
    Filed: January 17, 2003
    Publication date: June 12, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hidenari Otani, Kunihiko Suzuki, Shouji Satou
  • Publication number: 20030094648
    Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 22, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hidenari Otani, Kunihiko Suzuki, Shouji Satou
  • Publication number: 20030023566
    Abstract: The present invention proposes a safe and quick individual certification method using a portable terminal. When a portable terminal 30 sends a request for certification to a certification server 10, the certification server 10 transmits query code for certification to the portable terminal 30. The portable terminal 30 transmits said query code to the certification server 10 via a reader 21 or the like and also via a sales management server 23 to be certified. The certification server 10 verifies the query code to that generated in the past, and returns a result of verification and personal data required by the sales management server 23 to the sales management server 23.
    Type: Application
    Filed: September 3, 2002
    Publication date: January 30, 2003
    Inventors: Tomonori Fujisawa, Shouji Satou