Abstract: A system comprising a plurality of common bus systems, each of which has a given priority of use for peripheral units, and a unique transfer unit. When data is transferred from a unit of one of the common bus systems to a unit of another common bus system, the transfer unit acts to supervise the transfer, avoid conflicting requests and satisfy priority transfer requirements. In one embodiment the data is temporarily stored in the transfer control unit. In a second embodiment the transfer control equipment includes a circuit for processing the highest priority transmission and a response circuit for generating dummy responses for lower priority transmissions, e.g. invalid or wait responses. In a third embodiment the transfer control unit includes a request circuit for sending the transfer request signal to another common bus and a circuit for assuring that the time period during which the address and data which is sent is within a predetermined time.