Patents by Inventor Shouli Hsia

Shouli Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6495408
    Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: December 17, 2002
    Assignee: LSI Logic Corporation
    Inventors: Shouli Hsia, Jiunn-Yann Tsai
  • Patent number: 6046113
    Abstract: A method of removing an outer layer from an inner surface during semiconductor fabrication. A portion of the outer layer (50) may be anisotropically etched. A remaining portion of the outer layer (55) may then be wet etched without impairing the inner surface (12).
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: April 4, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Qi-Zhong Hong, Shouli Hsia
  • Patent number: 6034401
    Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: March 7, 2000
    Assignee: LSI Logic Corporation
    Inventors: Shouli Hsia, Jiunn-Yann Tsai