Abstract: The present invention disclosures a phase change memory unit, wherein comprising from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit is a longitudinally arranged column, which comprises: a cylindrical selector layer, a circular barrier layer and a circular phase change material layer form inside to outside; wherein, the bottom electrode, the heating electrode and the circular phase change material layer are sequentially connected, and the selector layer is connected to the top electrode. The present invention using trench sidewall deposition or via filling, forming the cylindrical phase change unit which is a circular nested structure, which can improve reliability of a device, greatly reduce volume of a phase change operation area and heat energy required, thus heating efficiency is improved obviously, the power consumption of the device is reduced, and high-density storage is realized.

Abstract: A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties.

Abstract: A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties.

Abstract: The present invention provides an infrared pixel structure and a hybrid imaging device which use comb-shaped top plates and bottom plates to form capacitors. The upper electrode has a non-fixed end such that the infrared sensitive element in the upper electrode generates thermal stress and deforms when absorbing the infrared light, which changes the capacitance of the capacitors formed by the top plates and the bottom plates to achieve infrared detection and increase the device sensitivity. Furthermore, the infrared pixel structure can be used in an infrared light and visible light hybrid imaging device to achieve visible light imaging and infrared imaging in a same silicon substrate, so as to increase the imaging quality.

Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Abstract: A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers.

Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Abstract: A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers.