Abstract: A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.

Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.

Abstract: Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.

Abstract: Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.

Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.