Abstract: In a semiconductor memory device, a data holding unit is disposed separately from the first and second floating gate transistors. A voltage difference is generated by the difference between the threshold voltages of the first and second floating gate transistors, and the voltage difference is stored in the form of a binary data. Thereafter, the first and second floating gate transistors are turned off. Thus, a minute current which always flows through the first and second floating gate transistors in the conventional technique is prevented from being generated so that the power consumption is reduced. In addition, data is fetched from the data holding unit while the bias voltage generating units are turned off. Thus, the time period of operating the bias voltage generating units is eliminated so that the memory device can operate at a high speed.