Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: An IEEE 1149.1 standard based testing method used in packaging is disclosed. The method includes adding a TRD pin to each of n devices up to the IEEE 1149.1 standard. The TRD pins of the n devices are connected together to a common output terminal which is connected to a testing system. The first to m-th ones of the devices are tested by connecting the TDO and TRD pins of the m-th device and disconnecting the TDO and TRD pins of any one of the n devices other than the m-th, wherein m is a natural number that is smaller than or equal to n.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.

Abstract: A compression method for compressing an original test file is disclosed. The compression method includes the following steps: defining type modules; scanning the original test file line by line in bytes and matching data of the original test file with the type modules to determine types of the data; compressing continuous data of the same type in lines and representing each compressed portion with a thumbnail. The compression method enables a browser to read test files with a fast speed by compressing test files according to the types of data.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.