Patents by Inventor Shouzi Tanaka
Shouzi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7936036Abstract: A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the photodiode region and the floating diffusion region, and formed so that both ends of the gate electrode respectively overlap a part of the photodiode region and a part of the floating diffusion region; and an inactive layer formed in a region located in a bottom portion and sidewall portions of the trench isolation region. An impurity concentration in a region located under the gate electrode in the inactive layer is lower than that in a region other than the region located under the gate electrode in the inactive layer.Type: GrantFiled: May 1, 2009Date of Patent: May 3, 2011Assignee: Panasonic CorporationInventors: Shouzi Tanaka, Ryohei Miyagawa
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Patent number: 7745859Abstract: A solid-state image sensing apparatus has a signal storage portion of a second conductivity type provided within a substrate, a surface shield layer of the first conductivity type provided in a surface portion of the substrate which is located above the signal storage portion, a gate electrode provided over the substrate in adjacent relation to at least one end of the signal storage portion, and a drain region of the second conductivity type provided in a surface portion of the substrate which is on the side opposite to the surface shield layer when viewed from the gate electrode. A read control layer of the first conductivity type is further provided in a surface portion of the substrate which is located under the gate electrode in adjacent relation to one end of the surface shield layer.Type: GrantFiled: January 9, 2007Date of Patent: June 29, 2010Assignee: Panasonic CorporationInventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa, Kazunari Koga
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Patent number: 7728895Abstract: A solid-state image sensing device includes: a plurality of unit pixels 21 arranged in rows and columns each of which outputs a pixel signal according to incident light; and a plurality of floating diffusion portions 22 each of which receives the pixel signals. Each of the floating diffusion portions 22 is shared by two unit pixels 21 which are respectively arranged in adjacent rows and which are respectively adjacent columns.Type: GrantFiled: July 11, 2006Date of Patent: June 1, 2010Assignee: Panasonic CorporationInventors: Shouzi Tanaka, Ryouhei Miyagawa, Kazunari Koga, Takahiro Muroshima, Kenji Watanabe
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Patent number: 7719040Abstract: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).Type: GrantFiled: July 27, 2006Date of Patent: May 18, 2010Assignee: Panasonic CorporationInventors: Hiroki Nagasaki, Shouzi Tanaka
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Patent number: 7696546Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.Type: GrantFiled: January 17, 2008Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa
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Publication number: 20090278181Abstract: A solid-state image sensor includes: a trench isolation region; a photodiode region for converting incident light to signal charges and accumulating the signal charges therein; a floating diffusion region for accumulating the signal charges of the photodiode region; a gate electrode formed over the element formation region located between the photodiode region and the floating diffusion region, and formed so that both ends of the gate electrode respectively overlap a part of the photodiode region and a part of the floating diffusion region; and an inactive layer formed in a region located in a bottom portion and sidewall portions of the trench isolation region. An impurity concentration in a region located under the gate electrode in the inactive layer is lower than that in a region other than the region located under the gate electrode in the inactive layer.Type: ApplicationFiled: May 1, 2009Publication date: November 12, 2009Inventors: Shouzi TANAKA, Ryohei Miyagawa
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Patent number: 7518144Abstract: In an element for a MOS type solid-state imaging device, a leakage current caused by a stress generated in a vicinity of an element isolation region having an STI structure is reduced. The element for the MOS type solid-state imaging device comprises: a signal accumulation region 102, of a second conductivity type, provided in an interior of a semiconductor substrate or well 101 of a first conductivity type, for accumulating a signal charge generated by performing photoelectric convention; a gate electrode 104 provided on the semiconductor substrate or well 101; a drain region 105, of a second conductivity type, provided on a surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed; and an element isolation region 201 provided on the surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed. The element isolation region 201 has the STI structure, and a cavity 202 is formed in an interior of the element isolation region 201.Type: GrantFiled: January 17, 2007Date of Patent: April 14, 2009Assignee: Panasonic CorporationInventors: Tatsuya Hirata, Shouzi Tanaka
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Publication number: 20090045407Abstract: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).Type: ApplicationFiled: July 27, 2006Publication date: February 19, 2009Inventors: Hiroki Nagasaki, Shouzi Tanaka
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Patent number: 7485939Abstract: An inversion layer is formed in a part as a boundary between (a) a defect control layer formed along a trench surface for isolating pixel calls and (b) a photo diode. The defect control layer is a P-type, and the photo diode and the inversion layer are N-type. Here, an impurity concentration in the inversion layer is at least twice as high as an impurity concentration in the photo diode.Type: GrantFiled: May 17, 2006Date of Patent: February 3, 2009Assignee: Panasonic CorporationInventors: Shouzi Tanaka, Ryohei Miyagawa
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Publication number: 20080273105Abstract: A solid-state image sensing device includes: a plurality of unit pixels 21 arranged in rows and columns each of which outputs a pixel signal according to incident light; and a plurality of floating diffusion portions 22 each of which receives the pixel signals. Each of the floating diffusion portions 22 is shared by two unit pixels 21 which are respectively arranged in adjacent rows and which are respectively adjacent columns.Type: ApplicationFiled: July 11, 2006Publication date: November 6, 2008Inventors: Shouzi Tanaka, Ryouhei Miyagawa, Kazunari Koga, Takahiro Muroshima, Kenji Watanabe
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Publication number: 20080173911Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.Type: ApplicationFiled: January 17, 2008Publication date: July 24, 2008Inventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa
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Publication number: 20070241374Abstract: A solid-state image sensing apparatus has a signal storage portion of a second conductivity type provided within a semiconductor substrate or a well each of a first conductivity type to store a signal charge obtained through a photoelectric conversion, a surface shield layer of the first conductivity type provided in a surface portion of the semiconductor substrate or the well which is located above the signal storage portion, a gate electrode provided over the semiconductor substrate or the well in adjacent relation to at least one end of the signal storage portion, and a drain region of the second conductivity type provided in a surface portion of the semiconductor substrate or the well which is on the side opposite to the surface shield layer when viewed from the gate electrode.Type: ApplicationFiled: January 9, 2007Publication date: October 18, 2007Inventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa, Kazunari Koga
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Publication number: 20070221973Abstract: A solid-state imaging device includes: a plurality of photodiodes arranged in a matrix on a semiconductor substrate 1 for storing a signal charge converted from incident light; MOS transistors for reading the signal charge stored in the photodiode, an element isolation region for isolating the photodiode from the MOS transistors, an implanted isolation layer formed below the element isolation region, and an impurity region surrounding the photodiode, the sides and bottom of the element isolation region and the implanted isolation layer. The implanted isolation layer covers the sides and bottom of the element isolation region. The solid-state imaging device can efficiently suppress the sensitivity degradation caused by the outflow of electric charge.Type: ApplicationFiled: March 20, 2007Publication date: September 27, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroki Nagasaki, Shouzi Tanaka, Motonari Katsuno
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Publication number: 20070200148Abstract: In an element for a MOS type solid-state imaging device, a leakage current caused by a stress generated in a vicinity of an element isolation region having an STI structure is reduced. The element for the MOS type solid-state imaging device comprises: a signal accumulation region 102, of a second conductivity type, provided in an interior of a semiconductor substrate or well 101 of a first conductivity type, for accumulating a signal charge generated by performing photoelectric convention; agate electrode 104 provided on the semiconductor substrate or well 101; a drain region 105, of a second conductivity type, provided on a surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed; and an element isolation region 201 provided on the surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed. The element isolation region 201 has the STI structure, and a cavity 202 is formed in an interior of the element isolation region 201.Type: ApplicationFiled: January 17, 2007Publication date: August 30, 2007Inventors: Tatsuya Hirata, Shouzi Tanaka
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Publication number: 20060261386Abstract: An inversion layer is formed in a part as a boundary between (a) a defect control layer formed along a trench surface for isolating pixel calls and (a) a photo diode. The defect control layer is a P-type, and the photo diode and the inversion layer are N-type. Here, an impurity concentration in the inversion layer is at least twice as high as an impurity concentration in the photo diode.Type: ApplicationFiled: May 17, 2006Publication date: November 23, 2006Inventors: Shouzi Tanaka, Ryohei Miyagawa