Abstract: This semiconductor device includes a plurality of sets of gate trenches, a plurality of gate electrodes, a plurality of field plate electrodes, a gate wiring, and a source wiring. The plurality of field plate electrodes each include two terminals connected to the source wiring. An outer peripheral gate wiring part of the gate wiring includes a gate finger that extends along a first direction in a plan view, and an inner gate wiring part includes a gate finger that extends along a second direction in a plan view. A first set of gate trenches extend along the first direction in a plan view and cross the gate finger, and a second set of gate trenches extend in the second direction in a plan view and cross the gate finger.