Patents by Inventor Shoyu Watanabe
Shoyu Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10062758Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: GrantFiled: August 19, 2014Date of Patent: August 28, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 9874596Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.Type: GrantFiled: March 10, 2014Date of Patent: January 23, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shoyu Watanabe, Akihiro Koyama, Shigehisa Yamamoto, Yukiyasu Nakao, Kazuya Konishi
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Patent number: 9502553Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: July 1, 2015Date of Patent: November 22, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9293572Abstract: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.Type: GrantFiled: June 24, 2010Date of Patent: March 22, 2016Assignee: Mitsubishi Electric CorporationInventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Shiro Hino, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Masayuki Imaizumi
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Publication number: 20160003889Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.Type: ApplicationFiled: March 10, 2014Publication date: January 7, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shoyu WATANABE, Akihiro KOYAMA, Shigehisa YAMAMOTO, Yukiyasu NAKAO, Kazuya KONISHI
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Publication number: 20150303297Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa MIURA, Shuhei NAKATA, Kenichi OHTSUKA, Shoyu WATANABE, Naoki YUTANI
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Patent number: 9105715Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: April 30, 2009Date of Patent: August 11, 2015Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9006819Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.Type: GrantFiled: February 8, 2011Date of Patent: April 14, 2015Assignee: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
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Publication number: 20140353686Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: ApplicationFiled: August 19, 2014Publication date: December 4, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 8860039Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: GrantFiled: April 7, 2011Date of Patent: October 14, 2014Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 8629498Abstract: In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film.Type: GrantFiled: July 15, 2009Date of Patent: January 14, 2014Assignee: Mitsubishi Electric CorporationInventors: Shoyu Watanabe, Shuhei Nakata, Naruhisa Miura
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Patent number: 8513735Abstract: A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow.Type: GrantFiled: June 30, 2009Date of Patent: August 20, 2013Assignee: Mitsubishi Electric CorporationInventors: Shuhei Nakata, Shoyu Watanabe, Kenichi Otsuka, Naruhisa Miura
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Patent number: 8492836Abstract: In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.Type: GrantFiled: October 14, 2009Date of Patent: July 23, 2013Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Shiro Hino, Akihiko Furukawa
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Publication number: 20130168700Abstract: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.Type: ApplicationFiled: June 24, 2010Publication date: July 4, 2013Applicant: Mitsubishi Electric CorporationInventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Shiro Hino, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Masayuki Imaizumi
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Publication number: 20130020587Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.Type: ApplicationFiled: February 8, 2011Publication date: January 24, 2013Applicant: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
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Publication number: 20130020586Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: ApplicationFiled: April 7, 2011Publication date: January 24, 2013Applicant: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 8350270Abstract: A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.Type: GrantFiled: March 4, 2009Date of Patent: January 8, 2013Assignee: Mitsubishi Electric CorporationInventors: Shoyu Watanabe, Shuhei Nakata, Kenichi Ohtsuka
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Publication number: 20120205669Abstract: In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.Type: ApplicationFiled: October 14, 2009Publication date: August 16, 2012Applicant: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Shiro Hino, Akihiko Furukawa
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Publication number: 20120061688Abstract: In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film.Type: ApplicationFiled: July 15, 2009Publication date: March 15, 2012Applicant: Mitsubishi Electric CorporationInventors: Shoyu Watanabe, Shuhei Nakata, Naruhisa Miura
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Publication number: 20110284874Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: ApplicationFiled: April 30, 2009Publication date: November 24, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani