Patents by Inventor Shozo Hosoda

Shozo Hosoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6110287
    Abstract: A plasma processing method in which a high-frequency power is supplied to a processing chamber in which an object to be processed is mounted, thereby producing a plasma in the processing chamber, and the object is processed in an atmosphere of the plasma, wherein the high-frequency power is subjected to modulation by a low-frequency power. In one embodiment a plasma is produced in a processing chamber by using an electric power with a direction of current changed with passing of time, and the object to be processed is processed in an atmosphere of the plasma, wherein a power having a basic frequency is subjected to frequency modulation with a frequency equal to n-times (n=an integer) the basic frequency. In a plasma processing apparatus of the invention, while a process gas is supplied to a processing chamber via a first gas introducing hole formed in an electrode, an object to be processed, which is held on an opposed electrode, is subjected to plasma processing.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: August 29, 2000
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Izumi Arai, Yoshifumi Tahara, Hiroshi Nishikawa, Yoshinobu Mitano, Shunichi Iimuro, Kazuo Fukasawa, Yutaka Miura, Shozo Hosoda
  • Patent number: 5779803
    Abstract: An apparatus for subjecting a semiconductor wafer having an uncovered marginal portion, from which a photoresist film is removed, to an anisotropic etching. The apparatus comprises a process chamber which can be set to a vacuum. Upper and lower electrodes opposite to each other are provided in the process chamber. An etching gas is made into plasma between these electrodes. An electrostatic chuck is arranged on the lower electrode. A wafer is mounted on the electrostatic chuck. A ring made of dielectric material, movable upward and downward, is arranged between the electrodes. A central portion of the ring is formed as a hood having a recessed shape corresponding to the marginal portion of the wafer. During the etching, the hood covers the marginal portion of the wafer under a plasma sheath, so as to be out of contact with the wafer, thereby preventing the marginal portion of the wafer from being etched.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: July 14, 1998
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Yoichi Kurono, Shigeki Tozawa, Shozo Hosoda
  • Patent number: 5611655
    Abstract: A vacuum process apparatus includes a convey chamber having a plurality of loading/unloading ports and an airtight structure kept in a vacuum when a target object is conveyed, at least one preliminary vacuum chamber connected to the convey chamber through a loading/unloading port, a plurality of vacuum process chambers connected to the convey chamber through the loading/unloading ports and each having a vacuum process mechanism, a plurality of gate valves for opening/closing the plurality of loading/unloading ports, and a multi-joint arm member, arranged in the convey chamber, for conveying the target object between the convey chamber and the vacuum process chambers, and between the convey chamber and the preliminary chamber. The convey chamber is evacuated through a bearing for a pivot shaft of the multi-joint arm member.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: March 18, 1997
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Yoshio Fukasawa, Shozo Hosoda, Tatsuya Nakagome, Takashi Tozawa, Koji Suzuki, Yasumasa Ishihara, Minoru Aoyagi, Mahito Kajihara
  • Patent number: 5578164
    Abstract: An apparatus for subjecting a semiconductor wafer having an uncovered marginal portion, from which a photoresist film is removed, to an anisotropic etching. The apparatus comprises a process chamber which can be set to a vacuum. Upper and lower electrodes opposite to each other are provided in the process chamber. An etching gas is made into plasma between these electrodes. An electrostatic chuck is arranged on the lower electrode. A wafer is mounted on the electrostatic chuck. A ring made of dielectric material, movable upward and downward, is arranged between the electrodes. A central portion of the ring is formed as a hood having a recessed shape corresponding to the marginal portion of the wafer. During the etching, the hood covers the marginal portion of the wafer under a plasma sheath, so as to be out of contact with the wafer, thereby preventing the marginal portion of the wafer from being etched.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: November 26, 1996
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Yoichi Kurono, Shigeki Tozawa, Shozo Hosoda
  • Patent number: 4782037
    Abstract: Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.
    Type: Grant
    Filed: October 30, 1986
    Date of Patent: November 1, 1988
    Assignees: Hatachi, Ltd, Hitachi Microcomputer Engineering Ltd.
    Inventors: Akihiro Tomozawa, Yoku Kaino, Shigeru Shimada, Nozomi Horino, Yoshiaki Yoshiura, Osamu Tsuchiya, Shozo Hosoda