Patents by Inventor Shozo Ochi

Shozo Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11892248
    Abstract: A cooling unit includes a unit main body including a bottom portion, a peripheral wall portion rising from the peripheral edge of the bottom portion, and a seal for sealing an opening of the unit main body. The unit main body is joined to the seal through a plasticized region, and a void is defined in the peripheral wall portion of the unit main body.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 6, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shozo Ochi, Masato Maede, Tomonari Nebashi, Ryo Ishikawa
  • Publication number: 20220397353
    Abstract: A cooling unit includes a unit main body including a bottom portion, a peripheral wall portion rising from the peripheral edge of the bottom portion, and a sealing body for sealing an opening of the unit main body. The unit main body is joined to the sealing body through a plasticized region, and a void is formed at a position close to the unit main body with respect to a center of the plasticized region.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 15, 2022
    Inventors: SHOZO OCHI, MASATO MAEDE, TOMONARI NEBASHI, RYO ISHIKAWA
  • Patent number: 11381767
    Abstract: A solid-state imaging device includes a solid-state imaging element and a substrate fixed to the solid-state imaging element by a sealing resin on a surface on an opposite side of a light receiving surface of the solid-state imaging element, an outer edge of the substrate seen from the light receiving surface side of the solid-state imaging element is positioned within an outer edge of the solid-state imaging element and an outer edge of the sealing resin seen from the light receiving surface side of the solid-state imaging element is positioned within the outer edge of the solid-state imaging element. The sealing resin includes a first sealing resin and a second sealing resin not contacting the first sealing resin to seal the components.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 5, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyokazu Itoi, Takeru Tamari, Daisuke Sakurai, Shozo Ochi
  • Publication number: 20220045027
    Abstract: A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 ?m and less than or equal to 700 ?m.
    Type: Application
    Filed: July 1, 2021
    Publication date: February 10, 2022
    Inventors: SHOZO OCHI, HIDETOSHI KITAURA
  • Patent number: 10790250
    Abstract: A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 29, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daisuke Sakurai, Takeru Tamari, Shozo Ochi
  • Publication number: 20200195867
    Abstract: A solid-state imaging device includes a solid-state imaging element and a substrate fixed to the solid-state imaging element by a sealing resin on a surface on an opposite side of a light receiving surface of the solid-state imaging element, an outer edge of the substrate seen from the light receiving surface side of the solid-state imaging element is positioned within an outer edge of the solid-state imaging element and an outer edge of the sealing resin seen from the light receiving surface side of the solid-state imaging element is positioned within the outer edge of the solid-state imaging element. The sealing resin includes a first sealing resin and a second sealing resin not contacting the first sealing resin to seal the components.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: KIYOKAZU ITOI, TAKERU TAMARI, DAISUKE SAKURAI, SHOZO OCHI
  • Patent number: 10365446
    Abstract: An optical module structure includes a main substrate, an interposer substrate electrically connected to the main substrate via a first protruding electrode, a first communication LSI electrically connected to the interposer substrate via a second protruding electrode, an IC element electrically connected to the interposer substrate via a lateral-surface connection terminal of the interposer substrate and via a third protruding electrode, an Si bench substrate electrically connected to the IC element via a fourth protruding electrode and via a lateral-surface connection terminal of the Si bench substrate, an optical element electrically connected to the Si bench substrate via a fifth protruding electrode, and an optical fiber optically connected via an optical waveguide formed on the Si bench substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 30, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shozo Ochi, Daisuke Sakurai
  • Publication number: 20190181110
    Abstract: A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 13, 2019
    Inventors: Daisuke SAKURAI, Takeru TAMARI, Shozo OCHI
  • Publication number: 20190137708
    Abstract: An optical module structure includes a main substrate, an interposer substrate electrically connected to the main substrate via a first protruding electrode, a first communication LSI electrically connected to the interposer substrate via a second protruding electrode, an IC element electrically connected to the interposer substrate via a lateral-surface connection terminal of the interposer substrate and via a third protruding electrode, an Si bench substrate electrically connected to the IC element via a fourth protruding electrode and via a lateral-surface connection terminal of the Si bench substrate, an optical element electrically connected to the Si bench substrate via a fifth protruding electrode, and an optical fiber optically connected via an optical waveguide formed on the Si bench substrate.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 9, 2019
    Inventors: Shozo OCHI, Daisuke SAKURAI
  • Patent number: 9041221
    Abstract: An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 26, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shozo Ochi, Kazuya Ushirokawa, Keiichi Kusumoto, Takashi Yamada, Ken Yasue
  • Patent number: 8745859
    Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
  • Publication number: 20130277862
    Abstract: An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.
    Type: Application
    Filed: September 12, 2011
    Publication date: October 24, 2013
    Applicant: Panasonic Corporation
    Inventors: Shozo Ochi, Kazuya Ushirokawa, Keiichi Kusumoto, Takashi Yamada, Ken Yasue
  • Publication number: 20120293965
    Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicant: Panasonic Corporation
    Inventors: Shozo OCHI, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
  • Patent number: 8031127
    Abstract: The semiconductor memory module incorporating antenna includes a wiring board (11) having a connection terminal (17) connected with a control semiconductor element (16) and arranged at a position exposed to the surface of an outer case (15), and a terminal electrode (18) for antenna connection connected with the control semiconductor element (16) and arranged in the outer case (15); a semiconductor storage element (12) mounted on one side of the wiring board (11); and a loop-like antenna (13) and an antenna terminal electrode (20) formed on the other side of the wiring board (11) along the outer peripheral thereof, the wiring board (11) includes at least one magnetic body layer (14) and the terminal electrode (18) for antenna connection is connected with the antenna terminal electrode (20).
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Hidenobu Nishikawa, Hiroshi Sakurai
  • Patent number: 8025237
    Abstract: An antenna built-in module which incorporates an antenna, is thin and excellent in antenna characteristics, a card type information device and a method for manufacturing the same are provided. A wiring board (110) which has a wiring pattern (120) and in which an electronic component is mounted on at least one surface thereof, a magnetic substance (160) embedded in the other surface of the wiring board (110), an antenna pattern (170) provided on the magnetic substance (160), the wiring pattern (120) of the wiring board (110) and the antenna terminal electrode of the antenna pattern (170) are connected by a conductive via (200).
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: September 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Norihito Tsukahara, Yutaka Nakamura, Hirohisa Tanaka
  • Patent number: 7924228
    Abstract: A storage medium with built-in antenna includes circuit board on which semiconductor element is placed, first and second magnetic layers sandwiching semiconductor element and circuit board, and first and second antenna coils disposed on first and second magnetic layers. First and second antenna coils are connected in parallel on a flexible sheet. First and second antenna coils are folded at the sides of first and second magnetic layers, respectively, and electrically connected to semiconductor element.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi
  • Patent number: 7775446
    Abstract: Card type information device includes wiring board having a wiring pattern with an electronic component mounted on a first face of wiring board and an antenna connecting electrode, antenna board having antenna pattern with antenna terminal electrode formed on a first face of antenna board, magnetic material placed between wiring board and antenna board confronting each other, flexible wiring board for coupling the antenna connecting electrode to antenna terminal electrode, and housing for accommodating wiring board, antenna board, magnetic material, and flexible wiring board. Wiring board and antenna board are made from one and the same insulating motherboard.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Shozo Ochi, Osamu Uchida, Shigeaki Sakatani, Daisuke Sakurai, Masato Mori, Hiroshi Sakurai, Hidenobu Nishikawa
  • Publication number: 20100163630
    Abstract: An antenna built-in module which incorporates an antenna, is thin and excellent in antenna characteristics, a card type information device and a method for manufacturing the same are provided. A wiring board (110) which has a wiring pattern (120) and in which an electronic component is mounted on at least one surface thereof, a magnetic substance (160) embedded in the other surface of the wiring board (110), an antenna pattern (170) provided on the magnetic substance (160), the wiring pattern (120) of the wiring board (110) and the antenna terminal electrode of the antenna pattern (170) are connected by a conductive via (200).
    Type: Application
    Filed: November 8, 2006
    Publication date: July 1, 2010
    Applicant: Matsushita Electric Industrial Co., Ltd
    Inventors: Shozo Ochi, Norihito Tsukahara, Yutaka Nakamura, Hirohisa Tanaka
  • Publication number: 20100052996
    Abstract: A storage medium with built-in antenna includes circuit board on which semiconductor element is placed, first and second magnetic layers sandwiching semiconductor element and circuit board, and first and second antenna coils disposed on first and second magnetic layers. First and second antenna coils are connected in parallel on a flexible sheet. First and second antenna coils are folded at the sides of first and second magnetic layers, respectively, and electrically connected to semiconductor element.
    Type: Application
    Filed: July 10, 2006
    Publication date: March 4, 2010
    Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi
  • Publication number: 20090301771
    Abstract: A conductive bump formed on an electrode of an electronic component. The conductive bump is composed of a first bump having one or more layers formed on the electrode and including resin containing at least a spherical-shaped conductive filler, and a second bump formed on an upper surface of the first bump and including photosensitive resin containing a scale-shaped conductive filler.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 10, 2009
    Inventors: Shozo Ochi, Kazuya Ushirokawa, Takayuki Higuchi