Patents by Inventor Shozo Ochi
Shozo Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11892248Abstract: A cooling unit includes a unit main body including a bottom portion, a peripheral wall portion rising from the peripheral edge of the bottom portion, and a seal for sealing an opening of the unit main body. The unit main body is joined to the seal through a plasticized region, and a void is defined in the peripheral wall portion of the unit main body.Type: GrantFiled: May 24, 2022Date of Patent: February 6, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shozo Ochi, Masato Maede, Tomonari Nebashi, Ryo Ishikawa
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Publication number: 20220397353Abstract: A cooling unit includes a unit main body including a bottom portion, a peripheral wall portion rising from the peripheral edge of the bottom portion, and a sealing body for sealing an opening of the unit main body. The unit main body is joined to the sealing body through a plasticized region, and a void is formed at a position close to the unit main body with respect to a center of the plasticized region.Type: ApplicationFiled: May 24, 2022Publication date: December 15, 2022Inventors: SHOZO OCHI, MASATO MAEDE, TOMONARI NEBASHI, RYO ISHIKAWA
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Patent number: 11381767Abstract: A solid-state imaging device includes a solid-state imaging element and a substrate fixed to the solid-state imaging element by a sealing resin on a surface on an opposite side of a light receiving surface of the solid-state imaging element, an outer edge of the substrate seen from the light receiving surface side of the solid-state imaging element is positioned within an outer edge of the solid-state imaging element and an outer edge of the sealing resin seen from the light receiving surface side of the solid-state imaging element is positioned within the outer edge of the solid-state imaging element. The sealing resin includes a first sealing resin and a second sealing resin not contacting the first sealing resin to seal the components.Type: GrantFiled: February 27, 2020Date of Patent: July 5, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kiyokazu Itoi, Takeru Tamari, Daisuke Sakurai, Shozo Ochi
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Publication number: 20220045027Abstract: A semiconductor device includes an insulation board, an electrode provided on the insulation board, a bonding layer provided on the electrode and made of a sintered body of metal particles having an average particle size of nano-order, and a semiconductor element bonded to the electrode via the bonding layer. A layer thickness of the bonding layer is greater than or equal to 220 ?m and less than or equal to 700 ?m.Type: ApplicationFiled: July 1, 2021Publication date: February 10, 2022Inventors: SHOZO OCHI, HIDETOSHI KITAURA
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Patent number: 10790250Abstract: A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.Type: GrantFiled: December 6, 2018Date of Patent: September 29, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Daisuke Sakurai, Takeru Tamari, Shozo Ochi
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Publication number: 20200195867Abstract: A solid-state imaging device includes a solid-state imaging element and a substrate fixed to the solid-state imaging element by a sealing resin on a surface on an opposite side of a light receiving surface of the solid-state imaging element, an outer edge of the substrate seen from the light receiving surface side of the solid-state imaging element is positioned within an outer edge of the solid-state imaging element and an outer edge of the sealing resin seen from the light receiving surface side of the solid-state imaging element is positioned within the outer edge of the solid-state imaging element. The sealing resin includes a first sealing resin and a second sealing resin not contacting the first sealing resin to seal the components.Type: ApplicationFiled: February 27, 2020Publication date: June 18, 2020Inventors: KIYOKAZU ITOI, TAKERU TAMARI, DAISUKE SAKURAI, SHOZO OCHI
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Patent number: 10365446Abstract: An optical module structure includes a main substrate, an interposer substrate electrically connected to the main substrate via a first protruding electrode, a first communication LSI electrically connected to the interposer substrate via a second protruding electrode, an IC element electrically connected to the interposer substrate via a lateral-surface connection terminal of the interposer substrate and via a third protruding electrode, an Si bench substrate electrically connected to the IC element via a fourth protruding electrode and via a lateral-surface connection terminal of the Si bench substrate, an optical element electrically connected to the Si bench substrate via a fifth protruding electrode, and an optical fiber optically connected via an optical waveguide formed on the Si bench substrate.Type: GrantFiled: November 5, 2018Date of Patent: July 30, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shozo Ochi, Daisuke Sakurai
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Publication number: 20190181110Abstract: A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.Type: ApplicationFiled: December 6, 2018Publication date: June 13, 2019Inventors: Daisuke SAKURAI, Takeru TAMARI, Shozo OCHI
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Publication number: 20190137708Abstract: An optical module structure includes a main substrate, an interposer substrate electrically connected to the main substrate via a first protruding electrode, a first communication LSI electrically connected to the interposer substrate via a second protruding electrode, an IC element electrically connected to the interposer substrate via a lateral-surface connection terminal of the interposer substrate and via a third protruding electrode, an Si bench substrate electrically connected to the IC element via a fourth protruding electrode and via a lateral-surface connection terminal of the Si bench substrate, an optical element electrically connected to the Si bench substrate via a fifth protruding electrode, and an optical fiber optically connected via an optical waveguide formed on the Si bench substrate.Type: ApplicationFiled: November 5, 2018Publication date: May 9, 2019Inventors: Shozo OCHI, Daisuke SAKURAI
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Patent number: 9041221Abstract: An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.Type: GrantFiled: September 12, 2011Date of Patent: May 26, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Shozo Ochi, Kazuya Ushirokawa, Keiichi Kusumoto, Takashi Yamada, Ken Yasue
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Patent number: 8745859Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.Type: GrantFiled: May 16, 2012Date of Patent: June 10, 2014Assignee: Panasonic CorporationInventors: Shozo Ochi, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
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Publication number: 20130277862Abstract: An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.Type: ApplicationFiled: September 12, 2011Publication date: October 24, 2013Applicant: Panasonic CorporationInventors: Shozo Ochi, Kazuya Ushirokawa, Keiichi Kusumoto, Takashi Yamada, Ken Yasue
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Publication number: 20120293965Abstract: A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: Panasonic CorporationInventors: Shozo OCHI, Yoshitake Hayashi, Kazuo Ohtani, Yosuke Maeba
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Patent number: 8031127Abstract: The semiconductor memory module incorporating antenna includes a wiring board (11) having a connection terminal (17) connected with a control semiconductor element (16) and arranged at a position exposed to the surface of an outer case (15), and a terminal electrode (18) for antenna connection connected with the control semiconductor element (16) and arranged in the outer case (15); a semiconductor storage element (12) mounted on one side of the wiring board (11); and a loop-like antenna (13) and an antenna terminal electrode (20) formed on the other side of the wiring board (11) along the outer peripheral thereof, the wiring board (11) includes at least one magnetic body layer (14) and the terminal electrode (18) for antenna connection is connected with the antenna terminal electrode (20).Type: GrantFiled: March 28, 2007Date of Patent: October 4, 2011Assignee: Panasonic CorporationInventors: Shozo Ochi, Hidenobu Nishikawa, Hiroshi Sakurai
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Patent number: 8025237Abstract: An antenna built-in module which incorporates an antenna, is thin and excellent in antenna characteristics, a card type information device and a method for manufacturing the same are provided. A wiring board (110) which has a wiring pattern (120) and in which an electronic component is mounted on at least one surface thereof, a magnetic substance (160) embedded in the other surface of the wiring board (110), an antenna pattern (170) provided on the magnetic substance (160), the wiring pattern (120) of the wiring board (110) and the antenna terminal electrode of the antenna pattern (170) are connected by a conductive via (200).Type: GrantFiled: November 8, 2006Date of Patent: September 27, 2011Assignee: Panasonic CorporationInventors: Shozo Ochi, Norihito Tsukahara, Yutaka Nakamura, Hirohisa Tanaka
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Patent number: 7924228Abstract: A storage medium with built-in antenna includes circuit board on which semiconductor element is placed, first and second magnetic layers sandwiching semiconductor element and circuit board, and first and second antenna coils disposed on first and second magnetic layers. First and second antenna coils are connected in parallel on a flexible sheet. First and second antenna coils are folded at the sides of first and second magnetic layers, respectively, and electrically connected to semiconductor element.Type: GrantFiled: July 11, 2006Date of Patent: April 12, 2011Assignee: Panasonic CorporationInventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi
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Patent number: 7775446Abstract: Card type information device includes wiring board having a wiring pattern with an electronic component mounted on a first face of wiring board and an antenna connecting electrode, antenna board having antenna pattern with antenna terminal electrode formed on a first face of antenna board, magnetic material placed between wiring board and antenna board confronting each other, flexible wiring board for coupling the antenna connecting electrode to antenna terminal electrode, and housing for accommodating wiring board, antenna board, magnetic material, and flexible wiring board. Wiring board and antenna board are made from one and the same insulating motherboard.Type: GrantFiled: February 26, 2007Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Shozo Ochi, Osamu Uchida, Shigeaki Sakatani, Daisuke Sakurai, Masato Mori, Hiroshi Sakurai, Hidenobu Nishikawa
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Publication number: 20100163630Abstract: An antenna built-in module which incorporates an antenna, is thin and excellent in antenna characteristics, a card type information device and a method for manufacturing the same are provided. A wiring board (110) which has a wiring pattern (120) and in which an electronic component is mounted on at least one surface thereof, a magnetic substance (160) embedded in the other surface of the wiring board (110), an antenna pattern (170) provided on the magnetic substance (160), the wiring pattern (120) of the wiring board (110) and the antenna terminal electrode of the antenna pattern (170) are connected by a conductive via (200).Type: ApplicationFiled: November 8, 2006Publication date: July 1, 2010Applicant: Matsushita Electric Industrial Co., LtdInventors: Shozo Ochi, Norihito Tsukahara, Yutaka Nakamura, Hirohisa Tanaka
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Publication number: 20100052996Abstract: A storage medium with built-in antenna includes circuit board on which semiconductor element is placed, first and second magnetic layers sandwiching semiconductor element and circuit board, and first and second antenna coils disposed on first and second magnetic layers. First and second antenna coils are connected in parallel on a flexible sheet. First and second antenna coils are folded at the sides of first and second magnetic layers, respectively, and electrically connected to semiconductor element.Type: ApplicationFiled: July 10, 2006Publication date: March 4, 2010Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi
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Publication number: 20090301771Abstract: A conductive bump formed on an electrode of an electronic component. The conductive bump is composed of a first bump having one or more layers formed on the electrode and including resin containing at least a spherical-shaped conductive filler, and a second bump formed on an upper surface of the first bump and including photosensitive resin containing a scale-shaped conductive filler.Type: ApplicationFiled: June 3, 2009Publication date: December 10, 2009Inventors: Shozo Ochi, Kazuya Ushirokawa, Takayuki Higuchi