Patents by Inventor Shozo Satake

Shozo Satake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5564033
    Abstract: An external memory unit for a data processing system has a plurality of detachable memory media. Data is written in parallel to the memory media. Since the positions of the memory media can be switched, reference information is written in each of the media during an initialization process. Once initialized, the data can be read from and written to the memory media regardless of their current and former positions in the external memory unit. The reference information has sequence information indicating the position of a memory medium in a sequence when data is first written to a group of media as part of an operation that subdivides data and writes the subunits to the group. The name of the group is also included in the reference information. When a subsequent read or write operation is requested, the group information is used to determine if all of the media required for executing the request are present in the external memory unit, and if so, the operation is executed.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: October 8, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Toshitsugu Takekuma, Shozo Satake, Asayoshi Kawashita
  • Patent number: 4511812
    Abstract: A programmable logic array comprises an AND array for producing AND term outputs on a plurality of AND term lines, an OR array which receives the AND term output of the AND array as inputs thereto, and an AND term disregarding array connected to the AND term lines to selectively invalidate the AND term outputs. The AND term disregarding array functions to disregard one of the AND terms on which a program defect is present.
    Type: Grant
    Filed: June 15, 1982
    Date of Patent: April 16, 1985
    Assignee: Hitachi, Ltd.
    Inventor: Shozo Satake
  • Patent number: 4263545
    Abstract: An AC test is disclosed which measures a time from the application of an input pulse on an input terminal of a circuit under consideration to the appearance of an output pulse on an output terminal of the circuit. The input terminal of the circuit is connected with an input driver through a first relay and connected with a pulse generator through a second relay. The opening-closing sequence of the first and second relays is selected such that the input terminal of the circuit is connected with at least one of the pulse generator and the input driver during a status setting of the circuit and during the application of the pulse. As a result, the occurrence of noises at the time of change-over operation between the pulse generator and the input driver is suppressed.
    Type: Grant
    Filed: May 10, 1979
    Date of Patent: April 21, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Shozo Satake, Katsuhiko Takizawa