Patents by Inventor Shozo Shirota

Shozo Shirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5488006
    Abstract: A method of manufacturing a one-chip microcomputer with mask ROM and a one-chip microcomputer with EPROM, wherein a plurality of photomasks for photomechanical process and/or photomask data can be used in common. According to this method, because of the common use of the photomasks and/or photomask data, it becomes able to make uniform the layout, size and electric characteristic of chips.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: January 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shozo Shirota
  • Patent number: 5357472
    Abstract: For directly observing from the outside the electrical characteristics of a memory cell, i.e., a voltage-current characteristic and threshold voltage in a non-volatile semiconductor memory device, there are provided same bit train selector means 5 for selecting and switching on a plurality of bit train selecting FETs(QB.sub.o, QB.sub.1. . . , QB.sub.n) each for interconnecting an external terminal 4 to which arbitrary voltage is applied and respective memory cell arrays 1a, 1b, . . . , 1n with each other and forming a current path extending from a specific memory cell FET (Q.sub.1) on the same bit train memory cell array to the external terminal, and a power supply circuit for supplying variable voltage to a gate of the specific memory cell FET (Q.sub.i). Hereby, there are improved the yield of articles and the accuracy of failure article analyses.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shozo Shirota
  • Patent number: 5343431
    Abstract: A semiconductor memory apparatus capable of judging whether or not there is short circuit between bit lines 1 (word lines) by respectively connecting a plurality of the bit lines 1 (word lines), wired in parallel to each other so as to select memory cell for outputting data from a memory cell array 4 in which memory cells are arranged in the form of matrix, connected to power source potential line 14 and ground potential line 16 alternately through switching elements 5, 6 respectively, thereby measuring leak current flowing between the both lines 14 and 16 in the state where the switching elements 5, 6 are ON, a testing apparatus being provided with a power source 10 supplying to each of the switching elements 5, 6 of this semiconductor memory apparatus and with an ampere meter 11 for measuring leak current, and relieving method for the semiconductor memory apparatus from short circuit between the bit lines (word lines) by making the switching elements 5, 6 ON as well as applying overvoltage to the bit lines
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: August 30, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahiro Ohtsuka, Shozo Shirota