Abstract: An interface circuit providing serial access to a non-volatile memory in an integrated circuit has at least two memory-access scan registers and at least one selection scan register coupled in common to a data input terminal of the integrated circuit. These registers are also coupled through a multiplexer to a data output terminal of the integrated circuit. The memory-access scan registers receive serial data such as address data and data to be written in the non-volatile memory at the specified addresses. The selection scan register receives a code for selecting the memory-access scan registers. Serial access to the non-volatile memory is speeded up because the memory-access scan registers can be accessed individually.

Abstract: An interface circuit providing serial access to a non-volatile memory in an integrated circuit has at least two memory-access scan registers and at least one selection scan register coupled in common to a data input terminal of the integrated circuit. These registers are also coupled through a multiplexer to a data output terminal of the integrated circuit. The memory-access scan registers receive serial data such as address data and data to be written in the non-volatile memory at the specified addresses. The selection scan register receives a code for selecting the memory-access scan registers. Serial access to the non-volatile memory is speeded up because the memory-access scan registers can be accessed individually.

Abstract: An interface circuit providing serial access to a non-volatile memory in an integrated circuit has at least two memory-access scan registers and at least one selection scan register coupled in common to a data input terminal of the integrated circuit. These registers are also coupled through a multiplexer to a data output terminal of the integrated circuit. The memory-access scan registers receive serial data such as address data and data to be written in the non-volatile memory at the specified addresses. The selection scan register receives a code for selecting the memory-access scan registers. Serial access to the non-volatile memory is speeded up because the memory-access scan registers can be accessed individually.

Abstract: There is provided an address decoder which allows a high-speed operation without causing a malfunction. When a pre-charge signal is in a state of being set at a logical level of "0", an address driver is brought into a state of being held at "1". When the pre-charge signal is in a state of being set to a logical level "1", the address driver outputs a drive signal pair which becomes positive phase and negative phase of an address signal to each of the drive signal lines. A detection circuit is connected to each signal line of at least one drive signal pair among a plurality of signal pairs at an end portion of the signal lines on the side opposite to the address driver. The decoding circuits all have the same circuit structure. Eight input terminals are connected to either one of the signal lines and are uniformly disposed along the drive signal lines.

Abstract: A pulse counter has a programmable prescaler that divides the frequency of an input clock pulse signal by a factor designated by a code signal. A counter counts the prescaled clock pulse signal output by the programmable prescaler to generate a count output. A code generator encodes the count output to generate the code signal that controls the programmable prescaler.

Abstract: A medical image recording apparatus according to the present invention in which the optical path length of the optical system is extremely short and the number of mechanical operating mechanisms is reduced electronically scans an LED array assembly (14) having a plurality of one-dimensionally arranged LED's with an LED array controller (28) and feeds a photosensitive recording medium (15) in a direction perpendicular to the direction of arrangement of the LED's by means of a motor (17) controlled by a film feed controller (29). The LED array controller and the film feed controller are operated on the basis of commands given from a scanning controller (27) which is controlled by a CPU.

Abstract: The present invention relates to a CRT multiformat camera which photographs CRT images onto photographic media of either film or photoprint in photographic conditions automatically set according to a selected photographic media type and has a feature of including photographing media discriminator (1) which discriminates between photographic media, and photographing condition setting device (4) which sets photographic conditions to the camera and/or the CRT display unit according to the discriminating signal of said photographing media discriminator.

Abstract: Disclosed is an improved defrosting system in a compression refrigerator. According to this invention there is provided a defrosting system in which the liquid-phase refrigerant is extracted from upstream of the expansion valve to a defrosting tank which is maintained at an elevated temperature high enough to cause the refrigerant to change from the liquid to vapor phase, and the now vapor-phase refrigerant is supplied to the evaporator where the refrigerant lose its heat in changing from the vapor to liquid phase, and the now liquid-phase refrigerant returns to the defrosting tank. The refrigerant circulates until the evaporator has been completely defrosted.