Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.

Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.